Static Timing Analysis

• Analysis of the design for timing issues
• STA provides a faster and simpler way of checking and analyzing all the timing paths in a design for any timing violations.

Modelling of a gate level netlsit

• STA can be modeled for the following reasons

  • How the interconnect is modeled - Ideal interconnect, wire load model, global routes with approximate RCs, or real routes with accurate RCs
  • How clocks are modeled - ideal or propagated
  • Whether coupling between signals is included - whether any cross-talk noise is analyzed or not

Slew

 * Slew the rate of change
 * It is measured in terms of transition time
 * Transition time and slew are inversely related to each other

Skew

 * Difference in timing between two or more signals.
 * Clock Latency : Time taken from the clock to reach from clock start point to the clock end point. 
   * Source Latency and Network Latency 
 * Clock skew    : Difference in arrival times of clocks at different end points.

Clock Uncertainity

Clock Latency

Generated Clocks

a. Clock which is derived from the master clock.

1. If there's a /3 circuitry, once would define a generated clock definition at the output of this circuitry
2. Definingn a new clock as generated clock doesn't create a new clock domain and the generated clock is considered to be in phase with the master clock
3. In a master clock, clock definition point is the origin of the master clock
4. In a generated clock, clock definition point is the master clock
5. "The start point of a clock path is always the master clock definition point"
6. Advantage of generating a clock : " Source latency is not automatically included" b. Methods to create a generated clock using : -- "-edges" -- "create_generated_clock" -- "-invert" c. Clock latency for Generated Clocks
7. A source latency specified on a generated clock specifies the latency from the defition of the master clock to the definition of the generated clock.
8. Total clock latency (Generated Clock) = Source latency (Master + Generated clock ) + Network Latency (Generated Clock)

d. Typical Clock generation scenario

1. Assume an Oscillator which is external to the chip produces a low freq clock which is used as a reference clock by the on-chip PLL to generate a high-frequency low-jitter clock.
2. This clock is then fed to a clock divider that generates the required clocks for the ASIC
3. A master clock is defined for the referenc clock at the input pin where it enters the chip and a seocond master clock is defined at the output of the PLL.
4. PLL output clock has no phase relationship with the reference clock. Hence, output clock shouldn't be a generated clock of the reference clock.
5. All clocks generated by the clock divider logic are specified as generated clocks of the master clock at the PLL out-put.

Constraining the Input paths

1. STA cannot check any timing on a path that is not constrained. All paths must be constrained to enable 
   their analysis
2. Figure 7-21 shows an input path of the design under analysis (DUA). Flipflop UFF0 is external to the design and provides data to the flip-flop UFF1

which is internal to the design. The data is connected through the input port INP1. 3. The clock definition for CLKA specifies the clock period, which is the total amount of time available between the two flip-flops UFF0 and UFF1. 4. The time taken by the external logic is Tclk2q, the CK to Q delay of the launch flip-flop UFF0, plus Tc1, the delay through the external combinational logic. Thus, the delay specification on an input pin INP1 defines an external delay of Tclk2q plus Tc1.

5. set Tclk2q 0.9
   set Tc1 0.6
   set_input_delay -clock CLKA -max [expr Tclk2q + Tc1] [get_ports INP1]
6. The constraint specifies that the external delay on input INP1 is 1.5ns and this is with respect to the clock CLKA. Assuming the clock period for CLKA is 2ns, then the logic for INP1 pin has only 500ps (= 2ns - 1.5ns) available for propagating internally in the design. This input delay specification maps into the input constraint that Tc2 plus Tsetup of UFF1 must be less than 500ps for the flip-flop UFF1 to reliably capture the data launched by flip-flop UFF0. Note that the external delay above is specified as a max quantity

Constraining the output paths

1. Output delay is specified related to the capture clock
2. Total delay of the external logic is Tsetup + Tcq

Output must be ready at the output port before the shaded region starts and should be stable all the way through the shaded region

Timing path groups

1. In STA, the paths are timed based upon valid start points and valid endpoints. Valid start points : Input ports, clock pins of synchronous design Valid end points : Output ports and data input pins of synchronous devices

   i. from an input port to an output port.
   ii. from an input port to an input of a flip-flop or a memory.
   iii. from the clock pin of a flip-flop or a memory to an input of flipflop or a memory.
   iv. from the clock pin of a flip-flop to an output port.

2. Timing paths are sorted into path groups by the clock associated with the endpoint of the path.

3. STA and reporting are done separately on each path group.

Other important constraints to accurately model the environment of a design

1. Apart from 'create_clock', 'set_input_delay', and 'set_output_delay' there are few other constraints to perform accurate timing analysis. 
2. They are :
   A. For inputs :  
      a. set_drive   
 
         i. This command explicitly specifies a value for the drive resistance at the input pin of the DUA. \
        ii. The smaller the drive value, the higher the drive strength. \
       iii. A resistance value of 0 implies an infinite drive strength.

      b. set_driving_cell

         i. This offers a more convenient and accurate approach in describing the drive capability of a port. \
        ii. This is used to specify a cell driving an input port.\
       iii. It is also used to calculate the transition time at the first cell and to compute the delay from the input port to the first cell in the presence of any interconnect.

     c. set_input_transition
       
        i. This specification offers a convenient way of expressing the slew at an input port. \
       ii. A reference clock can optionally be specified.

    2. Above two commands are used to model the drive strength of the external source that drives an input port of the block. In the absence of these specifications, all inputs are assumed to have an infinite drive strength. 

    3. A slew value at an input is needed to determine the delay of the first cell in the input path. In the absence of this specification, an ideal transition value of 0 is assumed.
   
      

   B. For outputs:

      a. set_load

        i. This places a capacitive load on output ports to model the external load being 
           driven by the output port. Default value is 0. 

       ii. This load can be specified as an explicit capacitance value or as an input pin capacitance of a cell.

Design Rule Checks

1. These checks ensures that all ports and pins in the design meet the specified limits for transition time (slew) and capacitance.

     a. set_max_transition. 
   
           i. Transition time is computed as a part of delay calculation = drive resistance of pin * total capacitance of net
   
     b. set_max_capacitance
           i. Capacitance on a net is calculated by taking the sum of all the pin capacitances plus any IO load plus any interconnect capacitance on the net.
   

2. Other design rule checks are set_max_fanout and set_max_area. These checks usually apply for synthesis not for STA.

Virtual Clocks

    i. A virtual clock is a clock that exists but is not associated with any pin or port of the design. 

   ii. It is used as a reference in STA analysis to specify input and output delays relative to a clock.
   iii. This is defined with no specifications of the source port or pin.

Refining the Timing Analysis

i. Four common commands that are used to constraint the analysis space are as follows.

a. set_case_analysis

  i. This specifies a constant value on a pin of a call or an input port.

b. set_disable_timing

  i. This breaks a timing arc of a cell.

c. set_false_path

  i. This specifies paths that are not real which implies that these paths are not checked in STA

d. set_multicycle_path

  i. This specifies the paths that can take longer than one clock cycle

Specifying inactive signals

A. set_case_analysis

i. If certain signals have a constant value in a specific mode, it is better to give the constant values to STA. \

ii. This helps in reducing the analysis space in addition to not reporting any paths that are irrelevant.
iii. Such constant signals are specified by using the set_case_analysis specification.
iv. When a design can run on multiple clock, and the selection of appropriate clock is controlled by multiplexers. To make STA analysis easier and reduce CPU run time, it is beneficial to do STA for each clock selection separately.

Breaking Timing arcs

i. It is possible that certain path through a cell cannot occur. In such case, it is useful to break the timing arc between the pins or ports. \

ii. It is done using set_disable_timing SDC command.
iii. Another example of similar usage is to disable the minimum clock pulse width check of a fli-flop.

Point to point specification

i. set_max_delay

ii. set_min_delay

Path segmentation

i. Breaking up a timing path into smaller paths can be timed is referred to as path segmentation.\

ii. A timing path has a start point and an end point.
iii. Additional startpoints and endpoints on a timing path can be created using the set_input_delay and set_output_delay specifications.
iv. set_input_delay which defines a startpoint, is typically specified on an output of a cell.
v. set_output_delay which defines a new endpoint is typically specified on an input of a cell.