Robust Verification - kkanthan77/Static-Timing-Analysis GitHub Wiki

On-Chip Variation

• Process and environmental parameters may not be uniform across different portions of the die.

• Due to process variations, identical MOS transistors in different portions of the die may not have similar characteristics. These are due to process variations within a die.

• Different portions of the design may also see different power supply voltage and temperature. It is therefore possible that two regions of the same chip are not at identical PVT conditions. There differences arise due to many factors, including:

  On Chip Variations:

  • IR drop variation
  • Voltage threshold variation of the PMOS or the NMOS device
  • Channel length variation of PMOS or NMOS
  • Temperature variations due to local hot spots
  • Interconnect metal etch or thickness variations impacting the interconnect resistance or capacitance

• These variations can affect the wire delays and cell delays in different portions of the chip.

• OCV effect is typically more pronounced on clock paths as they travel longer distances in a chip.

• STA can include the OCV effect by derating the delays of specific paths, that is, by making those paths faster or slower and then validating the behaviour of the design with these variations.

• The cell delays or wire delays or both can be derated to model the effect of OCV.

• Cell and net delays can be derated using the set_timing_derate specification.

Common Path Pessimism (CPP) or Clock Reconvergence Pessimissm Removal (CRPR)

• Applying different derating for the launch and capture clock is overly pessimistic as in reality this part of the clock tree will really be at one PVT condition, either as a maximum path or a minimum path, but never both at the same time.

• The pessimism caused by different derating factors applied on the common part of the clock tree is called Common Path Pessimism (CPP).

• CPPR is the removal of artificially induced pessimism between the launch clock path and the capture clock path in timing analysis.

• CPP itself is the delay difference between along this common portion of the clock tree due to different deratings for launch and capture clock paths.

• The difference between the minimum and the maximum arrival times of the clock signal at the common point is the CPP.

• The common point is defined as the output pin of the last cell in the common portion of the clock tree.

  CPP = Late Arrival Time @ common point - Earliest Arrival time @ common point

• OCV variations modeled by these derating factors can increase the minimum clock period which in turn reduces the maximum frequency of operation of the design.

Analysis with OCV at worst PVT condition

TBD

HOLD analysis with OCV

TBD

Time Borrowing (Cycle Stealing)

• This occurs at a latch.

• In a latch, one edge of the clock makes the latch transparent, that is, it opens the latch so that output of the latch is the same as the data input; this clock edge is called the opening edge.

• The second edge of the latch closes the latch and data present at the input cannot be available at the output, this is called closing edge.

• Data should be ready at a latch input before the active edge if the clock. Since, a latch is transparent when the clock is active, data can arrive later than the active edge, that is, it can borrow times from the next cycle.

• If such time is borrowed, the time available for the following stage is reduced.

Observation

• The first rule in timing to a latch is that if the data arrives before the opening-edge of the latch, the behaviour is modeled exactly like a flip-flop.

• The second rule applies when the data signal arrives while the latch is transparent (between opening and closing edge). The output of the latch, rather than the clock pin, is used as the launch point for the next stage.

Clock Gating checks

• A clock gating check occurs when a gating signal control the path of a clock signal at a logic cell.

• One condition for a clock gating check is that the clock that goes through the cell must be used as a clock downstream.

• The downstream clock usage can be either as a flip-flop clock or it can fanout to an output port or as a generated clock that refers to the output of the gating cell as its master.

• If the clock is not used as a clock after the gating cell, then no clock gating check is inferred.

• Another condition for the clock gating check applies to the gating signal. The signal at the gating pin of the check should not be a clock or if it is a clock, it should not be used as a clock downstream.

Types of clock gating checks inferred

• Active-high clock gating check : Occurs when the gating cell has an and or a nand function
• Active-low clock gating check : Occurs when the gating cell has a nor or an or function

Power Gating

• Gating off the power supply to the inactive blocks.

• This process involves adding a header(PMOS) or footer(NMOS) MOS device in series with the power supply.

• During inactive mode, the gating MOS device is turned off which eliminates any active power dissipation in the logic block.

• During sleep mode, the only power dissipated through the header and footer mos devices is through the leakage.

• The footers and headers are normally implemented using multiple power gating cells which correspond to multiple MOS devices in parallel.

• The header and footer cells introduce a series of on resistance to the power supply.

• If the on resistance is not small, the IR drop through the gating MOS can affect the timing of the cells.

• In a nutshell, there should be adequate number of power gating cells in parallel to ensure minimal IR drop from the series on resistance in active mode.

Multi Vt cells

• These are used to trade-off speed with leakage.

• High Vt cells - > Less leakage, slow Low Vt cells - > High leakage, fast

• In most designs, the goal is to minimize the total power while achieving the desired operational speed.

• Implementing the design with High Vt cells will increase the power consumption even though it reduces the leakage.

High Performance block with high activity

• A scenario where a high performance block with high switching activity and the power is dominated by the active power.

• For such blocks, focusing only on reducing leakage power can cause the total power to increase, despite reducing the leakage power.

• In these cases, initial design should use low vt cells to meet the desired performance, and after the timing is met, cells along the paths which have positive timing slack can be changed into high vt cells, so that leakage can be reduced.

• Hence, the following is inferred for the usage of cells:

• Low vt cells - > can be used only along the critical path to meet timing
  High vt cells - > can be used along the non-critical timing paths

High performance block with low activity

• In this scenario, where switching is not that frequent, active power will not be a major contributor for the total power.

• In these cases, high vt cells can be used for the initial implementation of the logic.

• An exception is with clock tree which is always active and therefore built on standard (low vt) cells.

• After the implementation with high vt cells, to achieve timing along critical paths, cells can be replaced with low vt cells to achieve the timing.

Well bias

• Adding a slight values for both VDD and GND to PMOS and NMOS will reduce the leakage power but the speed of the cell is impacted.

• VDD + 0.5 V or VSS - 0.5V

• The timing in the cell libraries are generated by taking well bias into account.

• The only drawback is the usage of additional power supplies.

Backannotation

Annotation

• The process of keeping the schematic information up-to date with the layout is called annotation.

Back Annotation

• Updating the schematic to match our new layout, updating the data entries for the schematic based on the changes in the layout is called back annotation

Sign-off MEthedology

• The three main variable that determine a scenario are as follows
  • Parasitic corners
  • Operating mode
  • PVT corner

Parasitic corners

• Parasitics can be extracted at many corners. They are governed by the metal width and metal etch in the manufacturing process.

  • Typical

    • Nominal values for resistance and capacitance

  • Max C

    • Interconnect resistance is smaller than at typical corner.
    • Interconnect capacitance is maximum
    • This corner results in largest delay for paths with short nets and can be used for max path analysis.

  • Min C

    • Interconnect resistance is larger than the typical corner
    • Interconnect capacitance is minimum
    • This corner results in smallest delay for paths with short nets and can be used for min path analysis.

  • Max RC

    • A corner which maximizes interconnect RC product.
    • Results in larger etch which reduces the trace width.
    • Large resistance but smaller capacitance.
    • This corner has the largest delay for the paths with short nets and used for max path analysis.

  • Min RC

    • A corner which minimizes interconnect RC product.
    • Results in smaller etch which increases the trace width
    • Small resistance by larger than typical capacitance
    • This corner has the smallest path delay for the paths with long interconnects and can be used for min path analysis.

• Corner with large C results in smaller R Corner with small C results in larger R

  No single corner can map to an extreme value (worst case / best case)

• CWorst/ Cbest are for short nets RCWorst/ RCbest are for long nets

Operating modes

• Functional mode 1 ( High speed clocks )
• Functional mode 2 ( Slow clocks )
• Functional mode 3 ( sleep mode )
• Functional mode 4 ( debug mode )
• Test mode 1 ( scan capture )
• Test mode 2 ( scan shift)
• Test mode 3 ( bist mode )
• Test mode 4 ( jtag mode )

PVT corners

• WCS ( process : slow, Power supply : low , Temperature : High )
• BCF ( process : fast, Power supply : high, Temperature : low)
• Typical( process : typical,Power supply : nominal, Temperature : nominal)
• WCL ( process : Worst-case slow at cold, Power supply : low , Temperature : low)

Global Process Variations

• Also called as inter-die device variations

• Variations in the process parameters which impact all devices on a die similarly.

Local Process Variations

• Intra-die device variations

• Variations in the process parameters can effect the devices differently on a given die.

• This implies that identical devices placed side by side behaves differently on a same die.