Physical Design

• The process of converting a synthesized gate-level netlist into a layout

Inputs for Physical Design

Gate level Netlist (.v)

• A netlist is a representation of the connectivity and logical relationships between different components and elements within the design.

• Acts as a blueprint for hardware implementation. It specifies how components are interconnected, there by defining the circuit's functionality.

• It contains the information about the following

  • Components like flip-flops, gates and other logic cells.
  • Connections between the components that allow information to flow through the circuit
  • Circuit relationships like the logic gates and functions that describe how the inputs to the circuits are combined to produce the desired output
  • Timing information like how the delay values are associated with interconnections which are to ensure proper signal propagation and synchronization.

Synopsys Design constraints

• SDC file contains design constraints and timing assignments and this follows a TCL syntax

• Imagine designing a microprocessor where billions of transistors, each responsible for a specific task. The key to making this complex system work efficiently lies in precisely controlling the timing of the signals as they propagate through the circuit. This is where SDC plays a key role.

• The following constraints are given to the design using SDC file

  • Timing
  • Power
  • Area

• Few of the important constraints in SDC are as follows

A. Operating conditions

• set_operating_conditions

B. Wire Load Models

• set_wire_load_mode
• set_wire_load_model

C. System Interface

• set_driving_cells
• set_load
• set_input_transition
• set_fanout_load

D. Design Rule Constraints

• set_max_fanout
• set_maximum_transition
• set_max_capacitance
• set_min_capacitance

E. Timing Constraints

• create_clock
• create_generated_clock
  • can be created as a divided-by/ multiply-by/ an inverted clock
• group_path
• set_clock_uncertainity
• set_clock_latency
• set_input_delay
• set_output_delay
• set_clock_transition
• set_clock_groups

F. Timing Exceptions

• set_multi_cycle_path
  • Specifies the number of cycles the data path must have for setup and hold check.
• set_false_path
• set_max_delay
• set_min_delay

G. Area constraints

• set_max_area

H. Multivoltage and power optimization constraints

• create_voltage_area
• set_max_dynamic_power
• set_max_leakage_power
• set_level_shifter_treshold

Logical libraries (.lib)

• It is a representation of timing and power parameters associated with cells inside the standard cell library of a particular technology node.

• Characterization of cells under different PVT conditions results in .lib file

• This file contains timing models and data to calculate

  • I/O delay paths
  • Timing check values
  • Interconnect delays

• The common path of the .lib contains the following:

  • Library name and technology name
  • Units
  • Operating conditions (PVT) - Max, Min, or Typical
  • Based on the operating conditions, there are three different lib files max, min and typical corners.

• The second part of the .lib contain cell specific information for each cell.

  • Cell name
  • PG pin name
  • Area of cell
  • Leakage power with respect to input pin's logic state
  • Pin details
    • Name
    • Direction
    • Internal power
    • Capacitance
    • Rise and Fall values of capacitance
    • Fanout load

• Timing and power parameter of a cell is obtained by simulating the cell in different operating conditions and are represented in .lib file.

  • CCS (Composite Current Source) - Current source

    • Represents the behaviour of a cell as a composite of current sources.
    • Accounts for non-linear and time-dependent behaviour of transistor switching.

  • NLDM (Non Linear Delay Model) - Voltage source

    • Cell delay is modeled as a function of input transition time and output load capacitance. It uses look-up tables to represent the relationship.
    • In deep sub-micron nodes, it can't model the effects of signal integrity issues like cross-talk and often ignores the impact of voltage variation.
    • It is used where speed is more critical than accuracy.

Library Exchange Format (.lef)

• It contains the design rules for routing and the abstraction of the cells, no information about the internal netlist of the cells.

• This file contains the physical characteristics of the cells in a technology library and provides a standard way to exchange the data between the IC design tools.

• LEF is of two types

  • Technology LEF ( Cadence : .techlef & Synopsys : .tf )
  • Cell LEF

• Technology LEF contains the following information

  • Layer name
  • Layer type
  • Design rules : width, pitch, spacing, direction, min cut
  • Via definitions
  • Metal capacitance and resistance
  • Antenna factor

• Cell LEF

  • Macro Cell descriptions : class, origin, symmetry, site, size
  • Cell dimensions
  • Layout of pins and blockages
  • Pin direction

• Manufacturing grid

  • It is used for geometry alignment. When specified, shapes and cells placed in locations that snap to the manufacturing grid.

TLUP (Table Look-up) (.tlup)

• This is a binary table format that stores RC co-efficients.

• It contains advanced process effect that can be used to extract RC values from interconnects.

• The TLU+ models enable accurate RC extraction results by including the effect of width, space, density and temperature on the resistance coefficients.

• Main function of the TLU+ file:

  • RC parasitics calculation per unit length
  • These parasitics are used for calculating net delays
  • If this file is not given, values are extracted from .ITF file.
  • For loading TLUP file, we have to load three files Max TLU+, Min TLU+ and Map file.
  • Map file maps the .ITP file and .tf file of the layer and via names.

UPF

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