Common Design Issues - kkanthan77/Static-Timing-Analysis GitHub Wiki

Common Issues

Antenna Effect or Plasma Induced Gate Oxide damage

  • Gate Oxide of a MOS transistor is the most sensitive part and special care needs to taken to prevent it from getting damaged.

  • This arises due to the plasma etching process during the fabrication of VLSI chips.

  • Though this happens during the fabrication stage, fabrication lab provides the antenna rule file which must be checked and designed should be cleaned during the physical sign-off stage.

  • FEOL - Front End of the Line, this involves the fabrication of all MOS transistors.

  • BEOL - Back End of the Line, this involves the fabrication of metal interconnects. Antenna effect comes into picture during BEOL.

Plasma Etching

  • A process used to fabricate the metal interconnects.

  • This is a dry and anisotropic etching process, used for selective etching. It contains high energetic ions and radicals which get collected by the metal interconnects while the etching of metal interconnects.

Antenna Effect

  • The amount of charge accumulated depends on the surface of the interconnect.

  • These collected ions increase the potential of the interconnect and if the interconnect is connected to the poly gate, ultimately the potential of the gate will increase.

  • Due to the increased potential of the gate, a drainage path may be formed through the gate oxide to substrate to balance this extra charge accumulation.

  • If the accumulated charge is high, the drained path through the gate oxide may either breakdown the gate oxide which leads to the permanent damage of the MOSFET.

  • The metal interconnect which collects the plasma(ions) and is connected to the gate is basically termed as the antenna.

Methods to overcome Antenna Violation

  • a. Reduce the amount of charge accumulated and this is achieved by reducing the area of metal interconnect connected to the gate of a transistor.

  • b. Increase the gate area so that the ratio ( Metal Area/ Gate Area ) becomes lesser than the permitted ratio.

  • c. Provide an alternative path to get discharge the accumulated charges on the gate of the transistor which is the addition of the antenna diode.

Antenna Rule

  • Ratio of the metal area connected to the gate to the total area of the gate.

  • Antenna area/ Gate area < Maximum antenna ratio

Three basic techniques to prevent antenna violation

  • Metal hopping

    Break the lengthy metal into small pieces and using jumpers route them through other metal layers. This is called jumper insertion of metal hopping.

  • Floating gate attachment

    • Effective gate area can be increased by attaching a dummy transistors. This will decrease the antenna ratio and help meeting the antenna rule.
    • We attach the input of buffer/ inverter to the concerned net and leave the output floating. This will increase the effective gate area.
  • Antenna diode

    • Should be kept near to the gate and reverse biased.

Latch-up in CMOS

Latch-up

  • This is a condition where a low impedance path is formed between supply pin and ground.

image

  • NPN & PNP transistors are merged together

    • PNP -> Base is the collector of NPN
    • NPN -> Base is the collector of PNP

image

  • At output (low), suppose if there's a noise signal, then output goes below by 0.7v

Vout <= -0.7v

  • n+ is forward biased due to the applied potential.

image

  • Eventually, electron injection happens and will flow through the collector.

  • NWELL doping shouldn't be high, it affects PMOS doping concentration.

  • If NWELL doping is low, there will be considerable voltage drop

  • P+ region is at a potential of VDD-0.7v and is of forward biased. This will lead to the PN juntion to be forward biased.

image

  • The emitter of this PNP transistor will start injecting holes as it is forward biased. These holes will be collected as shown.

image

  • Since, the substrate doping is very low, there will be a potential drop as shown. This makes the n+ region (marked) will be at a potential of 0.7v higher than the ground potential. image

  • This makes the region to be forward biased and makes it injecting electrons.

  • Even after we remove the initial spike, this process can continue forever provided the resistances of NWELL and PWELL are sufficiently high.

  • The key factors in latchup issue are the two resistances.

image

  • For proper MOSFET performance, doping concentrations are kept low. Because of these low doping concentrations there are more chances of these parasitic PNP and NPN transistors get activated.

Overcoming Latch-up

  • Without adversely affecting the performance of these transistors, the gains (β) of these transistors are to be cut.

  • Deliberately, eradiate these devices by gold or platinum doping. They introduce deep wells in the semiconductor which kills the life time.

  • Current trend is to reduce the resistances without effecting the performance of the MOSFET.

  • By having highly doped region deep inside the PSUB or underneath the NWELL using ion implantation, the current finds least resistance.

  • MOSFET performance is not affected, because, doping is not coming anywhere nearby the depletion region. It can kill the parasitic transistors.

  • Epitaxial layer

    • MOSFET is usually based of bulk wafers and expitaxial wafers are more expensive.

    • Because of this issue, it is good to use epitaxial wafer.

    • Instead of using bulk on p type substrate, it is advised to use P on P+ layer.

image

  • Region (2) is more thicker than that of 1.

  • Path of the current will be flowing through (2) and current finds little resistance. Even if there exists initial fluctuation of charge carriers, there will not be any regeneration without modifying the performance of the MOSFET.

  • Retrograde wafer

    • By using ion implantation, a retrograde well is formed. Peak doping concentration is formed deep inside the wafer.

image

  • When electrons are injected, it flows through the retrograde well, where it encounters little resistance. No chance of voltage drop that triggers the PN junction. No regenerative feedback is formed.