AXI Protocol Overview:

AMBA (Advanced Microcontroller Bus Architecture) is open standard for communication and management of the functional blocks in SoC, provide different on chip communication protocols like CHI (Coherence Hub Interface), AXI (Advanced eXtensible Interface), ACE (Advanced Coherency Extension), AHB ( Advanced High Performance Bus), APB (Advanced Peripheral Bus) developed by ARM (Advanced RISC Machine ) . Flexibility of AMBA protocols is IP reuse for different SoC designs with different area, power and performance requirements.

As the AMBA protocols are widely used open standards which ensures compatibility between IPs of different suppliers for the SoC , with compatibility it enables low friction integration and reuse of IP which catalyse the faster time to market. The AMBA AXI protocol specification is defined to implement a high frequency, high bandwidth interface across a wide variety of applications in embedded, automotive and cellphones. It does not require complex bridge implementation for different peripheral devices. The AXI protocol includes some new features which extend previous versions and is compatible to complement CHI. The following diagram shows how AXI is used to interface an interconnect component.

There are 3 types of AXI4-Interfaces (AMBA 4.0):

AXI4 (Full AXI4): For high-performance memory-mapped requirements.
AXI4-Lite: For simple, low-throughput memory-mapped communication (for example, to and from control and status registers).
AXI4-Stream: For high-speed streaming data.

Why AXI Required?

AXI offers higher performance and throughput than AHB. There are 2 basic reasons why AXI may be faster are given below.

1. Simplex Vs Duplex Transfers

• AXI has completely independent channels for read/write, which enables full duplex mode of data transportation. That is to say read and writes can take place simultaneously, giving 2x boost over AHB in any circumstances. However this will ONLY be possible when the slave is able to process 1 read and 1 write operation simultaneously in 1 clock cycle. Which in many cases will be possible, e.g. if the slave is a dual port SRAM which can process 1 read and 1 write transaction simultaneously. Also in this example we are considering 1 Master and 1 Slave. But in case of multiple slaves, the master can send read transaction to 1 slave and write to other slave, even if the slave(s) cannot handle more than 1 transactions in single clock cycle.

• To make more clarity, in a system where there is only 1 master and only 1 slave, the slave is unable to process read and write in 1 single clock cycle simultaneously and both master and slave are in single synchronous clock domain with no clock delay between the master and the slave there wont be any difference in performance between AXI and AHB. The AXI will only consume more power and area.

2. When there are clock cycle delays between a Master and a responding slave.

• This is usually when the Master clock and slave clock is Async, and a there is a clock domain crossing bridge. In AXI case, since the system is able to issue outstanding transactions (OT), i.e. able to issue addresses without waiting for data to return, there is only a initial delay, and then the continuous flow of data follows. In AHB this is not possible. The AHB cannot issue another transaction, without first receiving the response to its only transaction, which it can issue at a time.

• It is to be noted again, that if there are no clock delays between a master and a slave, and if we assume only 1 master and 1 slave in the system, then again the AXI performance will be equal to AHB performance, if we are doing only reads or only writes.

AXI Protocol Features:

The key features of the AXI protocol are:

• separate address/control and data phases
• support for unaligned data transfers, using byte strobes
• uses burst-based transactions with only the start address issued
• separate read and write data channels, that can provide low-cost Direct Memory Access (DMA)
• support for issuing multiple outstanding addresses
• support for out-of-order transaction completion
• permits easy addition of register stages to provide timing closure.