| pclk |
Clock source |
Clock. The rising edge of PCLK times all transfer on the APB. |
| preset_n |
System bus equivalent |
Reset. The APB reset signal is active low. This signal is normally connected directly to the system bus reset signal |
| paddr |
APB bridge |
Address. This is the APB address bus.It can be up to 32 bits wide and is a data access or an instruction access. |
| pprot |
APB bridge |
Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access. |
| pselx |
APB bridge |
Select. The APB bridge unit generates this signal to each peripheral bus slave. It indicates that the slave device is selected and that a data transfer is required. There is a pselx signal for each slave. |
| penable |
APB bridge |
Enable. This signal indicates the second and subsequent cycle of an APB transfer. |
| pwrite |
APB bridge |
Direction. This signal indicates an APB write access when HIGH and an APB read access when LOW. |
| pwdata |
APB bridge |
Write data. This bus is driven by the peripheralbus bridge unit during the write cycle when pwrite is HIGH. This bus can be up to 32 bits wide. |
| pstrb |
APB bridge |
Write strobes. This signal indicates when byte lanes to update during a write transfer. There is one write strobe for each eight bits of the write data bus. Therefore, pstrb[n] corresponds to pwdata[(8n+7):(8n)]. Write strobes must not be active during a read transfer. |
| pready |
Slave interface |
Ready. The Slave uses this signal to extend an APB transfer. prdata Slave interface Read Data.The selected slave drives this bus during read cycles when pwrite is LOW. This bus can be up to 32-bits wide. |
| pslverr |
Slave interface |
This signal indicates a transfer failure. APB peripherals are not required to support the pslverr pin. This is true for both existing and new APB peripheral designs. Where a peripheral does not include this PIN then the appropriate input to the APB bridge is tied LOW. |