Trion Interface User Guide - jungle-elec/FireAnt GitHub Wiki

• GPIO Interface
  • GPIO Block
    • Input Mode
    • Output Mode
    • Inout Mode
    • Clock Output Mode
    • None
  • GPIO Bus Block
• Oscillator Block
  • About Oscillator
  • Using the Oscillator Block
• Simple PLL Clock
  • About the Simple PLL Inteface
  • PLL Pins
  • PLL Settings
  • Using Simple PLL clock

Trion T8 FPGAs have simple I/O interface with logic and a buffer. The GPIOs support the 3.3V LVTTL and 1.8V, 2.5V, 3.3V LVCMOS I/O standards. These GPIOs are grouped into banks with separate bank voltage V_CCIO for different I/O standards. For simplicity, FireAnt has bonded all banks to 3.3V. Each GPIO consists of I/O logic and I/O buffer. I/O logic connects the core logic to the I/O buffers. I/O buffers are located at the periphery of the device.

GPIO block defines the functionality of the GPIO pins. The mode selected determines the GPIO capabilities and configuration.

To create new GPIO block, right click on GPIO in the Designer Explorer and then click Create Block.

Specify the instance name, then PRESS ENTER to activate (you can validate the changes on Block Summary next to Block Editor before and after pressing ENTER. Next open Resource Assigner to assign a resource for the signal.

The Resource Assigner provides a table view of all GPIO resources in your chosen FPGA and information about them, such as whether they are used, the I/O bank, pad, and package pin, and the instance assigned to the resource.

To assign a resource:

1. Select an unused resource.
2. Click Assign Resource Button

Note: If the block you selected has a resource assigned, the software highlights it in the table. Before you can assign a new resource, click Clear Assigned Resource to remove the setting.

Next define the GPIO modes. There are five GPIO modes which are input, output, inout, clkout and none:

Use Input mode for input signals.

• Pin Name: The Pin Name must match the top level RTL design.
• Connection Type: Indicate whether you want to use the normal or alternate pin function. (This option only applies to pins that have alternate functions. Refer to the data sheet for your FPGA for pin information.) For example, FireAnt uses GPIOL_20 as PLL reference clock input. In this case, set the connection type to alternative when specifying your PLL instance.
• Register Option: Choose whether the input is registered. If you enable the register option, you must also define the input clock.
• Pull Option: Choose a weak pullup, pulldown, or none.
• Enable Schmitt Trigger: Optionally enable a Schmitt trigger.

Use output mode for output signals.

• Pin Name: The Pin Name must match the top level RTL design.
• Constant Output: Choose "1" for V_CC or "0" for GND. Otherwise, leave this option as none.
• Register Option: Choose whether the output is registered or has an inverted register. If you enable the register option, you must also define an output clock.
• Drive Strength: Choose the drive strength.

Drive Strength	IOH (mA)	IOL (mA)
1	14.4	8.0
2	19.1	10.5
3	23.9	13.3
4	28.7	15.8

Junction Temperature T_J = 25 ^oC, V_CCIO = 3.3V, power supply at nominal voltage.

• Enable Slew Rate: Optionally enable slew rate.

Use inout mode for bidirectional signals.

• Input / Output: Inout mode has the same options for the input and output as the input and output modes.
• Output Enable: Inout mode also has an output enable signal (optionally registered) to enable or disable the output buffer
  • Pin Name: The Pin Name must match the top level RTL design. Setting the output enable signal to high “1” in your RTL design enables the output buffer.
  • Register Option: Choose whether the Output Enable signal is registered. If you enable the register option, you must also define an output clock.

Use clkout mode for clock output signals. You do not need to name the pin, but you do need to choose the clock to be an output.

Use none for unused signals. Specify whether the unused signal should have a weak pullup (default) or pulldown.

Remember to Check Design and Generate Efinity Constraint File every time you change settings in Efinity Interface Designer.

The GPIO bus is an easy way to add a group of GPIO blocks and make settings for the signal group.

To create a GPIO Bus, right click on GPIO in the Designer Explorer and then click Create GPIO Bus.

Specify a bus Name, the bus Width, and the Mode (input, output, or inout) and click Next.

The wizard displays options for Input, Output, or Inout, depending on the mode you selected. Refer to the GPIO Block for a description of these options. Make your selections and click Next.

Review the bus properties and click Finish. The software adds the new bus under GPIO.

After you create a bus, you can make additional settings for each signal.

1. Expand GPIO > <bus name>.
2. Make any block-specific settings in the Block Editor.
3. Assign a resource for the signal using the Resource Assigner.

Remember to Check Design and Generate Efinity Constraint File every time you change settings in Efinity Interface Designer.

FireAnt has one low-frequency oscillator tailored for low-power operation. The oscillator runs at nominal frequency of 10 kHz. Designers can use the oscillator to perform always-on functions with the lowest power possible. Its output clock is available to the GCLK network.

To use the oscillator, right click on Oscillator in the Designer Explorer and then click Create Block.

Specify the property in Block Editor:

• Instance Name: Any name.
• Oscillator Resource: Only OSC_0 is available for FireAnt (Trion T8).
• Pin Name: The Pin Name must match the top level RTL design.

Remember to Check Design and Generate Efinity Constraint File every time you change settings in Efinity Interface Designer.

Trion T8 has one Simple PLL to synthesize clock frequencies. The PLL's reference clock input comes from a dedicated GPIO's alternate input pin (FireAnt: GPIOL_20). The PLL consists of a pre-divider counter (N counter), a feedback multiplier counter (M counter), post-divider counter (O counter), and an output divider per clock output.

The counter settings defined the PLL output frequency:

F_PFD = F_IN / N

F_VCO = F_PFD x M

F_OUT = F_VCO / (O x Output divider)

where:

• F_VCO is the voltage control oscillator frequency
• F_OUT is the output clock frequency
• F_IN is the reference clock frequency
• F_PFD is the phase frequency detector input frequency

Note:

• The reference clock F_IN must be between 10 and 50 MHz.
• The F_PFD input must be between 10 and 50 MHz.
• The F_VCO frequency must be between 500 and 1,500 MHz.

Port	Direction	Description
CLKIN	Input	Reference clock. This port is also a GPIO pin; the GPIO pins' alternate function is configured as a reference clock.
RSTN	Input	Active-low PLL reset signal. When asserted, this signal resets the PLL; when de-asserted, it enables the PLL. Connect this signal in your design to power up or reset the PLL. Assert the RSTN pin for a minimum pulse of 10 ns to reset the PLL.
CLKOUT0 / CLKOUT1 / CLKOUT2	Output	PLL output. The designer can route these signals as input clocks to the core's GCLK network.
LOCKED	Output	Goes high when PLL achieves lock; goes low when a loss of lock is detected. Connect this signal in your design to monitor the lock status. This signal is analog asynchronous.

Setting	Allowed Values	Notes
N counter	1-15 (integer)	Pre-divider
M counter	1-255 (integer)	Multiplier
O counter	1, 2, 4, 8	Post-divider
Output divider	2, 4, 8, 16, 32, 64, 128, 256	Output divider (independent clock output)

We set 50 MHz clock output with 33.33MHz reference clock in as example below:

To use the Simple PLL clock, right click on PLL in the Designer Explorer and then click Create Block.

Specify the property in Block Editor as below:

Property	Value	Notes
Instance Name	PLL_INST_1	Any name
PLL Resource	PLL_0	Only one option
Reset Pin Name	PLL_RSTN	The Reset Pin Name must match the top level RTL design
Locked Pin Name	PLL_LOCKED	The Locked Pin Name must match the top level RTL design
Reference Clock Frequency (MHz)	33.33
Multiplier (M)	24
Pre Divider (N)	1
Post Divider (D)	1
Enable Output Clock 0	Checked
Output Clock 0 Pin Name	PLL_CLKOUT	The Output Clock 0 Pin Name must match the top level RTL design
Output Clock 0 Output Divider	16
Enable Output Clock 1	Un-checked
Enable Output Clock 2	Un-checked

Create a GPIO block and assign GPIOL_20 to the block, config the settings as below:

• Instance Name: PLL_INST_1_CLKIN (or any name)
• Mode: Input
• Pin Name: PLL_INST_1_CLKIN
• Connection Type: alternative

For instruction to create a GPIO Block. Refer to GPIO Block.

Remember to Check Design and Generate Efinity Constraint File every time you change settings in Efinity Interface Designer.