Challenge #25 SPI interface - jtristan123/HW-for-AI-ML-ECE-410 GitHub Wiki

SPI week 8 challenge 25

Time to VIBE

after vibing with chatGPT this what was the task given to it:

  1. Compile your Verilog source using iverilog
  • Based on TOPLEVEL and VERILOG_SOURCES in the Makefile
  1. Run the Python testbench using cocotb
  • The file defined by MODULE = test_spi

  • This is where @cocotb.test() functions get executed

  1. Print output to your terminal
  • Including any print() results from Python

  • Any dut._signal.value reads and test pass/fail logs

Design flow:

Python (software) runs on a CPU

Verilog (hardware) runs in a simulated or physical FPGA-like block

You want to offload specific tasks to hardware, like:

A random number generator (LFSR-based)

Maybe other logic (e.g. mutations or selection if you go full genetic algorithm)

Communication is done over SPI

using Chatgpt for a high-level view of where a SPI goes:

+-----------------------+                       +--------------------------+
|   Python Program      |                       |     Verilog Module       |
|  (Running on CPU)     |                       |  (Simulated or in FPGA)  |
|-----------------------|      SPI (MOSI/MISO)  |--------------------------|
|                       |<--------------------->|                          |
| - Uses spidev or cocotb                       | - SPI Slave              |
| - Sends command: "Get RNG value"              | - Implements LFSR        |
| - Receives random number                      | - Sends back 8-bit data  |
|                       |                       |                          |
+-----------------------+                       +--------------------------+

Next Step:

Replace shift_reg in your SPI slave with an LFSR

Every 8-bit SPI read gives a new pseudo-random number Add another Python test to verify randomness in cocotb

Flow chart

You run:           make
        ↓
Makefile calls:    cocotb
        ↓
Cocotb launches:   Icarus Verilog (simulator)
        ↓
Icarus compiles and runs:
    - spi_slave.v (your Verilog module)
    - hooks in cocotb’s Python logic

        ↓
Cocotb executes:
    - test_spi.py (your Python test code)
    - this drives & checks SPI behavior live

Output vibe coding with ChatGPT

Seeded LFSR with: 00001100
LFSR Output  test_spi4.py[0]: 00001100
LFSR Output  test_spi4.py[1]: 00001100
LFSR Output  test_spi4.py[2]: 00011001
LFSR Output  test_spi4.py[3]: 00110010
LFSR Output  test_spi4.py[4]: 01100100
  1070.00ns INFO     cocotb.regression                  spi_send_receive passed
  1070.00ns INFO     cocotb.regression                  **************************************************************************************
                                                        ** TEST                          STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
                                                        **************************************************************************************
                                                        ** test_spi4.spi_send_receive     PASS        1070.00           0.00     436015.69  **
                                                        **************************************************************************************
                                                        ** TESTS=1 PASS=1 FAIL=0 SKIP=0               1070.00           0.01     190731.38  **
                                                        **************************************************************************************

so using SPI it sends a seed to the LSFR, then it sends back a random number, cocotb was used to test bench