Verilog Data Types - johnmichael31/Verilog-Data-Types GitHub Wiki

Verilog Data Types: Overview

The primary intent of data types in Verilog is to represent:

• Storage elements (e.g., flip-flop bits).
• Transmission elements (e.g., wires connecting logic gates).

Most data types can hold one of four values:

Value	Description
0	Logic zero / false condition.
1	Logic one / true condition.
x	Unknown logic value (could be 0 or 1).
z	High-impedance state (unconnected wire).

Hardware Analogies:

• 1 ≈ Power supply voltage (e.g., Vdd = 0.8V–3V).
• 0 ≈ Ground (0V).
• x ≈ Unknown state (not "don’t care").
• z ≈ Unconnected wire (high impedance).

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Nets vs. Variables

Feature	Nets (e.g., wire)	Variables (e.g., reg)
Purpose	Connect hardware components (no storage).	Model storage elements (e.g., flip-flops).
Example	wire a; (connects gates).	reg b; (holds values between assignments).
Width	Can be single-bit or vectors (e.g., wire [3:0]).	Same as nets.

Key Points:

• wire: Most common net type.

  wire net_11;          // Single-bit wire
  wire [3:0] n0;        // 4-bit wire vector
  

• Illegal: Redeclaring a net/variable.

  wire abc;
  wire abc;  // ❌ Error: Identifier "abc" previously declared.
  

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Variables in Detail

1. reg

   • Models storage (flip-flops) or combinational logic.
   • Example:

     reg [3:0] data;  // 4-bit register (stores values).
     

2. integer

   • 32-bit signed integer.
   • Example:

     integer count = 32'hCAFE1234;  // Stores hex values.
     

3. time

   • 64-bit unsigned (stores simulation time).
   • Example:

     time end_time = 50ns;  // Debugging time values.
     

4. real

   • Stores floating-point numbers.
   • Example:

     real float = 12.344;
     

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Strings in Verilog

• Stored in reg variables (1 byte per ASCII character).
• Rules:
  • If reg width < string length: Truncates leftmost bits.
  • If reg width > string length: Left-pads with zeros.

Examples:

reg [8*11:1] str1 = "Hello World";  // Fits exactly.
reg [8*5:1]  str2 = "Hello World";  // Truncates to "World".
reg [8*20:1] str3 = "Hello World";  // Pads with spaces: "         Hello World".

Simulation Output:

str1 = Hello World
str2 = World
str3 =          Hello World

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Example Code

module testbench;
  integer int_a = 32'hcafe_1234;
  real    real_b = 0.1234567;
  time    time_c;

  initial begin
    #20;                  // Advance simulation time.
    time_c = $time;       // Capture current time.
    $display("int_a = 0x%0h", int_a);
    $display("real_b = %0.5f", real_b);  // Prints 0.12346 (rounded).
    $display("time_c = %0t", time_c);    // Prints "20".
  end
endmodule

Simulation Log:

int_a = 0xcafe1234
real_b = 0.12346
time_c = 20

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Summary Table

Data Type	Width	Use Case	Example
wire	User-defined	Connections between logic gates.	wire [3:0] bus;
reg	User-defined	Storage/comb. logic.	reg [7:0] byte;
integer	32-bit	General-purpose integers.	integer i = 42;
time	64-bit	Simulation time tracking.	time t = $time;
real	64-bit	Floating-point numbers.	real pi = 3.14;

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This version improves clarity with tables, code blocks, and consistent formatting. Let me know if you'd like further refinements!