RC_Receiver - jofranco/multi-rotor-on-FPGA GitHub Wiki
Overview
The RC Receiver core is powered by a FrSKY X8R Receiver using the SBUS protocol. This core is responsible for parsing the raw serial UART data from the UART16550 IP core. This is accomplished by some bit masking that allows us to grab only the bits of interest with each transaction. Once the data is parsed into channels, the IP core scales the active channels for use in the PID controllers.
Interface
The RC_Receiver IP core takes in a uint8_t vector on a save S_axilite AXI interface of twenty five data bytes from the SBUS message received by the UART16550. The data is MSB aligned for easy decoding into the 18 channels by the UART16550 based on our configurations so this makes it simple to shift and mask. Once the data is masked and scaled, the channel bits are loaded onto a 16 bit fixed point master AXI interface the and sent to Flight_Main. The output only contains the used channels for the current configuration. This can be easily changed by the common configuration header file included in the project.
Function
As mentioned above, the RC_Receiver is responsible for parsing the 11 bit RC channels from the 25 SBUS data byes received on the AXI bus. We do not need all 25 of the bytes brought into the core. In this configuration using SBUS, we can check for valid messages easily and discard the bytes that are not needed. To do this the core checks to see if the first and the last data bytes match the start and stop criterion. If they do the core will then mask the channel data from the 22 data bytes contained in the packet of 25. We only use the first 6 for this build, however we have 18 channels available to us. The details of the start and stop bytes are outlined below for reference.
- START_BYTE = 0X0F
- STOP_BYTE = 0X00
The table below outlines the channels contained in the SBUS packet. Here the channels have been colored to indicated where the bit boundaries are for each channel. We have an odd number of bits at 11 for each channel, and each byte contains 8 so we must ensure we have the shifts and mask correct.
- 11 bits per channel
- channels color separated for effect
- channel bit mapping
- number format -> [channel #].[bit #]
The table indicates each bit location with a numeric mapping using the channel number and the bit location. The bits are shown MSB first in this table as that is how the data is aligned for us. The first 20 bytes contain the 16 channels that would have been analog as a serial packet. The last two bytes contain the two discrete cannels {0,1} and the status flags from the Taranis. The code snippet below shows how the bits are shifted and masked to attain each channel.
