We are starting with revision B based on this being an update to the original BeagleBone AI. However, because this board ended up being so different, we’ve decided to name it BeagleBone AI-64, rather than simply a new revision.

This is the initial engineering prototype release of the board. We will be tracking changes from this point forward.

1. Connect the small connector on the USB cable to the board as shown in Figure 3. The connector is on the bottom side of the board.

   Figure 3. USB Connection to the Board

   

2. Connect the large connector of the USB cable to your PC or laptop USB port.

3. The board will power on and the power LED will be on as shown in Figure 4 below.

   Figure 4. Board Power LED

   

4. When the board starts to the booting process started by the process of applying power, the LEDs will come on in sequence as shown in Figure 5 below. It will take a few seconds for the status LEDs to come on, so be patient. The LEDs will be flashing in an erratic manner as it begins to boot the Linux kernel.

   Figure 5. Board Boot Status

   

The board will appear around a USB Storage drive on your PC after the kernel has booted, which will take a round 10 seconds. The kernel on the board needs to boot before the port gets enumerated. Once the board appears as a storage drive, do the following:

1. Open the USB Drive folder.

2. Click on the file named start.htm

3. The file will be opened by your browser on the PC and you should get a display showing the Quick Start Guide.

4. Your board is now operational! Follow the instructions on your PC screen.

In order to use the board in this configuration, you will need the following accessories:

• (1) 5VDC 3A power supply.

• (1) Display Port monitor (or a recommended uDP to HDMI adapter. https://www.amazon.com/dp/B089GF8M87 has been tested and worked beautifully.)

• (1) uDP to DP cable.

• (1) USB keyboard and mouse.

• (1) powered USB HUB (OPTIONAL). The board has only two USB Type-A host ports, so you may need to use a powered USB Hub if you wish to add additional USB devices, such as a USB WiFi adapter.

• (1) M.2 WiFi module (OPTIONAL). For wireless connections, a USB WiFi adapter or a recommended M.2 WiFi module can provide wireless networking.

For an up-to-date list of confirmed working accessories please go to https://github.com/beagleboard/beaglebone-ai-64/wiki/Accessories.

1. Connect the monitor

   Figure 7. Connect microDP Cable to the Monitor

   

2. If you have an HDMI or VGA monitor connect your adapter as shown in. Figure 8 below from two perspectives.

   Figure 8. microDP to HDMI Adapter

   (insert pictures.)

3. I you have USB keyboard and mouse such as

   seen in Figure 9 below, you need to plug the receiver in the USB host port of the board as shown in [figure-10].

   Figure 9. USB Keyboard and Mouse

   

4. Connect the Ethernet Cable

   If you decide you want to connect to your local area network, an Ethernet cable can be used. Connect the Ethernet Cable to the Ethernet port as shown in Figure 12. Any standard 100M Ethernet cable should work.

   Figure 12. Ethernet Cable Connection

   

5. The final step is to plug in the DC power supply to the DC power jack as shown in Figure 13 below.

   Figure 13. External DC Power

   

6. The cable needed to connect to your display is a microHDMI to HDMI. Connect the microHDMI connector end to the board at this time. The connector is on the bottom side of the board as shown in Figure 14 below.

   Figure 14. Connect microDP Cable to the Board

   

   The connector is fairly robust, but we suggest that you not use the cable as a leash for your Beagle. Take proper care not to put too much stress on the connector or cable.

7. Booting the Board

   As soon as the power is applied to the board, it will start the booting up process. When the board starts to boot the LEDs will come on in sequence as shown in Figure 15 below. It will take a few seconds for the status LEDs to come on, so be patient. The LEDs will be flashing in an erratic manner as it boots the Linux kernel.

   Figure 15. Board Boot Status

   

   While the four user LEDS can be over written and used as desired, they do have specific meanings in the image that is shipped with the board once the Linux kernel has booted.

   • USER0 is the heartbeat indicator from the Linux kernel.

   • USER1 turns on when the microSD card is being accessed

   • USER2 is an activity indicator. It turns on when the kernel is not in the idle loop.

   • USER3 turns on when the onboard eMMC is being accessed.

8. A Booted System

   1. The board will have a mouse pointer appear on the screen as it enters the Linux boot step. You may have to move the physical mouse to get the mouse pointer to appear. The system can come up in the suspend mode with the monitor in a sleep mode.

   2. After a minute or two a login screen will appear. You do not have to do anything at this point.

   3. After a minute or two the desktop will appear. It should be similar to the one shown in Figure 16. HOWEVER, it will change from one release to the next, so do not expect your system to look exactly like the one in the figure, but it will be very similar.

   4. And at this point you are ready to go! Figure 16 shows the desktop after booting.

      Figure 16. Desktop Screen

      

9. Powering Down

   1. Press the power button momentarily.

   2. The system will power down automatically.

   3. Remove the power jack.

Figure 17 below shows the locations of the connectors, LEDs, and switches on the PCB layout of the board.

• DC Power is the main DC input that accepts 5V power.

• Power Button alerts the processor to initiate the power down sequence and is used to power down the board.

• 10/100 Ethernet is the connection to the LAN.

• Serial Debug is the serial debug port.

• USB Client is a USB-C connection to a PC that can also power the board.

• BOOT switch can be used to force a boot from the microSD card if the power is cycled on the board, removing power and reapplying the power to the board..

• There are four blue LEDS that can be used by the user.

• Reset Button allows the user to reset the processor.

• microSD slot is where a microSD card can be installed.

• microDP connector is where the display is connected to.

• USB Host can be connected different USB interfaces such as Wi-Fi, BT, Keyboard, etc.

Figure 18 below shows the locations of the key components on the PCB layout of the board.

• TI J721E DRA829/TDA4VM/AM752x is the processor for the board.

• *4GB LPDDR4L is the Dual Data Rate RAM memory.

• SMSC Ethernet PHY is the physical interface to the network.

• Micron eMMC is an onboard MMC chip that holds up to 16GB of data.

• uDP Framer provides control for a DP HDMI or DVI-D display with an adapter.

A single 512Gb x16 LPDDR4 4Gb memory device is used. The memory used is is:

• Q3222PM1WDGTK

A single 4KB EEPROM is provided on I2C0 that holds the board information. This information includes board name, serial number, and revision information. This is the not the same as the one used on the original BeagleBone. The device was changed for cost reduction reasons. It has a test point to allow the device to be programmed and otherwise to provide write protection when not grounded.

A single 16GB embedded MMC (eMMC) device is on the board. The device connects to the MMC1 port of the processor, allowing for 8bit wide access. Default boot mode for the board will be MMC1 with an option to change it to MMC0, the SD card slot, for booting from the SD card as a result of removing and reapplying the power to the board. Simply pressing the reset button will not change the boot mode. MMC0 cannot be used in 8Bit mode because the lower data pins are located on the pins used by the Ethernet port. This does not interfere with SD card operation but it does make it unsuitable for use as an eMMC port if the 8 bit feature is needed.

The board is equipped with a single microSD connector to act as the secondary boot source for the board and, if selected as such, can be the primary boot source. The connector will support larger capacity microSD cards. The microSD card is not provided with the board. Booting from MMC0 will be used to flash the eMMC in the production environment or can be used by the user to update the SW as needed.

As mentioned earlier, there are two boot modes:

• eMMC Boot…This is the default boot mode and will allow for the fastest boot time and will enable the board to boot out of the box using the pre-flashed OS image without having to purchase an microSD card or an microSD card writer.

• SD Boot…This mode will boot from the microSD slot. This mode can be used to override what is on the eMMC device and can be used to program the eMMC when used in the manufacturing process or for field updates.

Software to support USB and serial boot modes is not provided by beagleboard.org. Please contact TI for support of this feature.

A switch is provided to allow switching between the modes.

• Holding the boot switch down during a removal and reapplication of power without a microSD card inserted will force the boot source to be the USB port and if nothing is detected on the USB client port, it will go to the serial port for download.

• Without holding the switch, the board will boot try to boot from the eMMC. If it is empty, then it will try booting from the microSD slot, followed by the serial port, and then the USB port.

• If you hold the boot switch down during the removal and reapplication of power to the board, and you have a microSD card inserted with a bootable image, the board will boot from the microSD card.

NOTE: Pressing the RESET button on the board will NOT result in a change of the boot mode. You MUST remove power and reapply power to change the boot mode. The boot pins are sampled during power on reset from the PMIC to the processor. The reset button on the board is a warm reset only and will not force a boot mode change.

The main Power Management IC (PMIC) in the system is the TPS659411 and TPS659413 which is a single chip power management IC consisting of a linear dual-input power path, three step-down converters, and four LDOs. LDO stands for Low Drop Out. If you want to know more about an LDO, you can go to http://en.wikipedia.org/wiki/Low-dropout_regulator. If you want to learn more about step-down converters, you can go to http://en.wikipedia.org/wiki/DC-to-DC_converter

The system is supplied by a USB port or DC adapter. Three high-efficiency 2.25MHz step-down converters are targeted at providing the core voltage, MPU, and memory voltage for the board.

The step-down converters enter a low power mode at light load for maximum efficiency across the widest possible range of load currents. For low-noise applications the devices can be forced into fixed frequency PWM using the I2C interface. The step-down converters allow the use of small inductors and capacitors to achieve a small footprint solution size.

LDO1 and LDO2 are intended to support system standby mode. In normal operation, they can support up to 100mA each. LDO3 and LDO4 can support up to 285mA each.

By default only LDO1 is always ON but any rail can be configured to remain up in SLEEP state. In particular the DCDC converters can remain up in a low-power PFM mode to support processor suspend mode. The TPS659411 and TPS659413 offers flexible power-up and power-down sequencing and several house-keeping functions such as power-good output, pushbutton monitor, hardware reset function and temperature sensor to protect the battery.

For more information on the TPS659411 and TPS659413, refer to http://www.ti.com/product/TPS659411 and TPS659413[http://www.ti.com/product/TPS659411 and TPS659413.]

Figure 22 is the high level block diagram of the TPS659411 and TPS659413.

Figure 23 below shows how the DC input is connected to the TPS659411 and TPS659413.

A 5VDC supply can be used to provide power to the board. The power supply current depends on how many and what type of add-on boards are connected to the board. For typical use, a 5VDC supply rated at 1A should be sufficient. If heavier use of the expansion headers or USB host port is expected, then a higher current supply will be required.

The connector used is a 2.1MM center positive x 5.5mm outer barrel. The 5VDC rail is connected to the expansion header. It is possible to power the board via the expansion headers from an add-on card. The 5VDC is also available for use by the add-on cards when the power is supplied by the 5VDC jack on the board.

The board can also be powered from the USB port. A typical USB port is limited to 500mA max. When powering from the USB port, the VDD_5V rail is not provided to the expansion headers, so capes that require the 5V rail to supply the cape direct, bypassing the TPS659411 and TPS659413, will not have that rail available for use. The 5VDC supply from the USB port is provided on the SYS_5V, the one that comes from theTPS659411 and TPS659413, rail of the expansion header for use by a cape. Figure 24 is the connection of the USB power input on the PMIC.

The selection of either the 5VDC or the USB as the power source is handled internally to the TPS659411 and TPS659413 and automatically switches to 5VDC power if both are connected. SW can change the power configuration via the I2C interface from the processor. In addition, the SW can read theTPS659411 and TPS659413 and determine if the board is running on the 5VDC input or the USB input. This can be beneficial to know the capability of the board to supply current for things like operating frequency and expansion cards.

It is possible to power the board from the USB input and then connect the DC power supply. The board will switch over automatically to the DC input.

A power button is connected to the input of the TPS659411 and TPS659413. This is a momentary switch, the same type of switch used for reset and boot selection on the board.

If you push the button the TPS659411 and TPS659413 will send an interrupt to the processor. It is up to the processor to then pull thePMIC_POWER_EN pin low at the correct time to power down the board. At this point, the PMIC is still active, assuming that the power input was not removed. Pressing the power button will cause the board to power up again if the processor puts the board in the power off mode.

In power off mode, the RTC rail is still active, keeping the RTC powered and running off the main power input. If you remove that power, then the RTC will not be powered. You also have the option of using the battery holes on the board to connect a battery if desired as discussed in the next section.

If you push and hold the button for greater than 8 seconds, the PMIC will power down. But you must release the button when the power LED turns off. Holding the button past that point will cause the board to power cycle.

Four pads are provided on the board to allow access to the battery pins on the TPS659411 and TPS659413. The pads can be loaded with a 4x4 header or you may just wire a battery into the pads. In addition they could provide access via a cape if desired. The four signals are listed below in Table 3.

There is no fuel gauge function provided by the TPS659411 and TPS659413. That would need to be added if that function was required. If you want to add a fuel gauge, and option is to use 1-wire SPI or I2C device. You will need to add this using the expansion headers and place it on an expansion board.

NOTE: Refer to the TPS659411 and TPS659413 documentation
before connecting anything to these pins.

The power consumption of the board varies based on power scenarios and the board boot processes. Measurements were taken with the board in the following configuration:

• DC powered and USB powered

• monitor connected

• USB HUB

• 4GB Thumbdrive

• Ethernet connected @ 100M

• Serial debug cable connected

Table 4 is an analysis of the power consumption of the board in these various scenarios.

The current will fluctuate as various activates occur, such as the LEDs on and microSD/eMMC accesses.

The processor interacts with the TPS659411 and TPS659413 via several different signals. Each of these signals is described below.

Figure 25 shows the connections of each of the rails from the TPS659411 and TPS659413.

The power LED is a blue LED that will turn on once the TPS659411 and TPS659413 has finished the power up procedure. If you ever see the LED flash once, that means that theTPS659411 and TPS659413 started the process and encountered an issue that caused it to shut down. The connection of the LED is shown in Figure 25.

Figure 28 shows the interface between the TPS659411 and TPS659413 and the processor. It is a cut from the PDF form of the schematic and reflects what is on the schematic.

When voltage is applied, DC or USB, the TPS659411 and TPS659413 connects the power to the SYS output pin which drives the switchers and LDOs in the TPS659411 and TPS659413.

At power up all switchers and LDOs are off except for the VRTC LDO (1.8V), which provides power to the VRTC rail and controls the RTC_PORZn input pin to the processor, which starts the power up process of the processor. Once the RTC rail powers up, the RTC_PORZn pin, driven by the LDO_PGOOD signal from the TPS659411 and TPS659413, of the processor is released.

Once the RTC_PORZn reset is released, the processor starts the initialization process. After the RTC stabilizes, the processor launches the rest of the power up process by activating thePMIC_POWER_EN signal that is connected to the TPS659411 and TPS659413 which starts the TPS659411 and TPS659413 power up process.

The LDO_PGOOD signal is provided by theTPS659411 and TPS659413 to the processor. As this signal is 1.8V from the TPS659411 and TPS659413 by virtue of the TPS659411 and TPS659413 VIO rail being set to 1.8V, and the RTC_PORZ signal on the processor is 3.3V, a voltage level shifter, U4, is used. Once the LDOs and switchers are up on the TPS659411 and TPS659413, this signal goes active releasing the processor. The LDOs on the TPS659411 and TPS659413 are used to power the VRTC rail on the processor.

Figure 28 above shows two interfaces between the processor and theTPS659411 and TPS659413 used for control after the power up sequence has completed.

The first is the I2C0 bus. This allows the processor to turn on and off rails and to set the voltage levels of each regulator to supports such things as voltage scaling.

The second is the interrupt signal. This allows the TPS659411 and TPS659413 to alert the processor when there is an event, such as when the power button is pressed. The interrupt is an open drain output which makes it easy to interface to 3.3V of the processor.

This section covers three general power down modes that are available. These modes are only described from a Hardware perspective as it relates to the HW design.

Figure 29 is a high level block diagram of the processor. For more information on the processor, go to https://www.ti.com/product/TDA4VM.

Table 5 below shows a few of the high level features of the Jacinto processor.

Full documentation for the processor can be found on the TI website at https://www.ti.com/product/TDA4VM for the current processor used on the board. Make sure that you always use the latest datasheets and Technical Reference Manuals (TRM).

Figure 30is the crystal circuitry for the TDA4VM processor.

Figure 31 is the board reset circuitry. The initial power on reset is generated by the TPS659411 and TPS659413 power management IC. It also handles the reset for the Real Time Clock.

The board reset is the SYS_RESETn signal. This is connected to the NRESET_INOUT pin of the processor. This pin can act as an input or an output. When the reset button is pressed, it sends a warm reset to the processor and to the system.

On the revision A5D board, a change was made. On power up, the NRESET_INOUT signal can act as an output. In this instance it can cause the SYS_RESETn line to go high prematurely. In order to prevent this, the PORZn signal from the TPS659411 and TPS659413 is connected to the SYS_RESETn line using an open drain buffer. These ensure that the line does not momentarily go high on power up.

This change is also in all revisions after A5D.

LPDDR4 Memory

The BeagleBone AI-64 uses a single MT41K256M16HA-125 512MB LPDDR4 device from Micron that interfaces to the processor over 16 data lines, 16 address lines, and 14 control lines. On rev C we added the Kingston KE4CN2H5A-A58 device as a source for the LPDDR4 device.

The following sections provide more details on the design.

The design supports the standard DDR3 and LPDDR4 x16 devices and is built using the LPDDR4. A single x16 device is used on the board and there is no support for two x8 devices. The DDR3 devices work at 1.5V and the LPDDR4 devices can work down to

1.35V to achieve lower power. The LPDDR4 comes in a 96-BALL FBGA package with 0.8 mil pitch. Other standard DDR3 devices can also be supported, but the LPDDR4 is the lower power device and was chosen for its ability to work at 1.5V or 1.35V. The standard frequency that the LPDDR4 is run at on the board is 400MHZ.

Figure 32 is the schematic for the LPDDR4 memory device. Each of the groups of signals is described in the following lines.

Address Lines: Provide the row address for ACTIVATE commands, and the column address and auto pre-charge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop).

Bank Address Lines: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA.

CK and CK# Lines: are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

Clock Enable Line: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during powerdown. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA.

Chip Select Line: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA.

Input Data Mask Line: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ.

On-die Termination Line: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the LPDDR4 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA.

The LPDDR4 memory device and the DDR3 rails on the processor are supplied by theTPS659411 and TPS659413. Default voltage is 1.5V but can be scaled down to 1.35V if desired.

The VREF signal is generated from a voltage divider on theVDDS_DDR rail that powers the processor DDR rail and the LPDDR4 device itself. Figure 33 below shows the configuration of this signal and the connection to the LPDDR4 memory device and the processor.

The device used is one of two different devices:

• Micron MTFC4GLDEA 0M WT

• Kingston KE4CN2H5A-A58

The package is a 153 ball WFBGA device on both devices.

Figure 34 is the design of the eMMC circuitry. The eMMC device is connected to the MMC1 port on the processor. MMC0 is still used for the microSD card as is currently done on the original BeagleBone. The size of the eMMC supplied is now 4GB.

The device runs at 3.3V both internally and the external I/O rails. The VCCI is an internal voltage rail to the device. The manufacturer recommends that a 1uF capacitor be attached to this rail, but a 2.2uF was chosen to provide a little margin.

Pullup resistors are used to increase the rise time on the signals to compensate for any capacitance on the board.

The pins used by the eMMC1 in the boot mode are listed below in Table 6.

For eMMC devices the ROM will only support raw mode. The ROM Code reads out raw sectors from image or the booting file within the file system and boots from it. In raw mode the booting image can be located at one of the four consecutive locations in the main area: offset 0x0 / 0x20000 (128 KB) / 0x40000 (256 KB) / 0x60000 (384 KB). For this reason, a booting image shall not exceed 128KB in size. However it is possible to flash a device with an image greater than 128KB starting at one of the aforementioned locations. Therefore the ROM Code does not check the image size. The only drawback is that the image will cross the subsequent image boundary. The raw mode is detected by reading sectors #0, #256, #512, #768. The content of these sectors is then verified for presence of a TOC structure. In the case of a GP Device, a Configuration Header (CH)must be located in the first sector followed by a GP header. The CH might be void (only containing a CHSETTINGS item for which the Valid field is zero).

The ROM only supports the 4-bit mode. After the initial boot, the switch can be made to 8-bit mode for increasing the overall performance of the eMMC interface.

Figure 36 below is the design of the microSD interface on the board.

The signals MMC0-3 are the data lines for the transfer of data between the processor and the microSD connector.

The MMC0_CLK signal clocks the data in and out of the microSD card.

The MMCO_CMD signal indicates that a command versus data is being sent.

There is no separate card detect pin in the microSD specification. It uses MMCO_DAT3 for that function. However, most microSD connectors still supply a CD function on the connectors. In the BeagleBone AI-64 design, this pin is connected to theMMC0_SDCD pin for use by the processor. You can also change the pin to GPIO0_6, which is able to wake up the processor from a sleep mode when an microSD card is inserted into the connector.

Pullup resistors are provided on the signals to increase the rise times of the signals to overcome PCB capacitance.

Power is provided from the VDD_3V3B rail and a 10uF capacitor is provided for filtering.

Figure 38 shows the circuitry that is involved in the boot configuration process. On power up, these pins are read by the processor to determine the boot order. S2 is used to change the level of one bit from HI to LO which changes the boot order.

It is possible to override these setting via the expansion headers. But be careful not to add too much load such that it could interfere with the operation of the display interface or LCD panels. If you choose to override these settings, it is strongly recommended that you gate these signals with the SYS_RESETn signal. This ensures that after coming out of reset these signals are removed from the expansion pins.

Figure 40 shows the connections between the processor and the PHY. The interface is in the MII mode of operation.

This is the same interface as is used on the BeagleBone. No changes were made in this design for the board.

The off board side of the PHY connections are shown in Figure 41 below.

This is the same interface as is used on the BeagleBone. No changes were made in this design for the board.

Figure 42 shows the power, reset, and lock connections to the LAN8710A PHY. Each of these areas is discussed in more detail in the following sections.

There are mode pins on the LAN8710A that sets the operational mode for the PHY when coming out of reset. These signals are also used to communicate between the processor and the LAN8710A. As a result, these signals can be driven by the processor which can cause the PHY not to be initialized correctly. To ensure that this does not happen, three low value pull up resistors are used. Figure 43 below shows the three mode pin resistors.

This will set the mode to be 111, which enables all modes and enables auto-negotiation.

The maximum resolution supported by the BeagleBone AI-64 is 1280x1024 @ 60Hz. Table 9 below shows the supported resolutions. Not all resolutions may work on all monitors, but these have been tested and shown to work on at least one monitor. EDID is supported on the BeagleBone AI-64. Based on the EDID reading from the connected monitor, the highest compatible resolution is selected.

Audio is limited to CEA supported resolutions. LCD panels only activate the audio in CEA modes. This is a function of the specification and is not something that can be fixed on the board via a hardware change or a software change.

insert processor Display Port framer doc here

insert processor Display Port V-interface doc here

insert processor Display Port C-interface doc here

insert processor Display Port interrupt doc here

insert processor Display Port audio doc here

guesing this doesn’t exist on this device

insert processor Micro Display Port connector doc here

U8 is a switch that allows the power to the connector to be turned on or off by the processor. It also has an over current detection that can alert the processor if the current gets too high via theUSB1_OC signal. The power is controlled by the USB1_DRVBUS signal from the processor.

U9 is the ESD protection for the signals that go to the connector.

FB7 andFB8 were added to assist in passing the FCC emissions test. The USB1_VBUS signal is used by the processor to detect that the 5V is present on the connector. FB7 is populated and FB8 is replaced with a .1 ohm resistor.

The features of the PRU-ICSS include:

Two independent programmable real-time (PRU) cores:

• 32-Bit Load/Store RISC architecture

• 8K Byte instruction RAM (2K instructions) per core

• 8K Bytes data RAM per core

• 12K Bytes shared RAM

• Operating frequency of 200 MHz

• PRU operation is little endian similar to ARM processor

• All memories within PRU-ICSS support parity

• Includes Interrupt Controller for system event handling

• Fast I/O interface

– 16 input pins and 16 output pins per PRU core. (Not all of these are accessible on the BeagleBone AI-64).

Figure 49 is a high level block diagram of the PRU-ICSS.

Both PRU 0 and PRU1 are accessible from the expansion headers. Some may not be useable without first disabling functions on the board like LCD for example. Listed below is what ports can be accessed on each PRU.

PRU0

• 8 outputs or 9 inputs

PRU1

• 13 outputs or 14 inputs

• UART0_TXD, UART0_RXD, UART0_CTS, UART0_RTS

Table 11 below shows which PRU-ICSS signals can be accessed on the BeagleBone AI-64 and on which connector and pins they are accessible from. Some signals are accessible on the same pins.

[table-12] shows the pin bindings for P8 and P9 expansion headers. Signals can be connected to theese connectors based on setting the pin mux on the processor, but this is the default settings on power up. The SW is responsible for setting the default function of each pin. There are some signals that have not been listed here. Refer to the processor documentation for more information on these pins and detailed descriptions of all of the pins listed. In some cases there may not be enough signals to complete a group of signals that may be required to implement a total interface.

The BALL NUMBER Identifier is the pin number in the processor documentation.

The PIN No. column is the pin number on the expansion header.

The ADDRESS column is the pin CONFIGURATION address??? for each pin.

The MUXMODE[14:0] SETTINGS are the possible pin configurations.

NOTE: DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.

NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.

There is a single USB Host connector on the board and is shown in Figure 53 below.

Figure 53. USB Host Connector

The port is USB 2.0 HS compatible and can supply up to 500mA of current. If more current or ports is needed, then a HUB can be used.

Each board has a debug serial interface that can be accessed by using a special serial cable that is plugged into the serial header as shown in Figure 54 below.

Figure 54. Serial Debug Header

Two signals are provided, TX and RX on this connector. The levels on these signals are 3.3V. In order to access these signals, a FTDI USB to Serial cable is recommended as shown in Figure 55 below.

The cable can be purchased from several different places and must be the 3.3V version TTL-232R-3V3. Information on the cable itself can be found direct from FTDI at:

http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL232R_CABLES.pdf

Pin 1 of the cable is the ai-64 wire. That must align with the pin 1 on the board which is designated by the white dot next to the connector on the board.

Refer to the support WIKI http://elinux.org/BeagleBoneBlack for more sources of this cable and other options that will work.

Table is the pinout of the connector as reflected in the schematic. It is the same as the

FTDI cable which can be found at

http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdf

with the exception that only three pins are used on the board. The pin numbers are defined in Table 14. The signals are from the perspective of the board.

Table 14. J1 Serial Header Pins

Figure 56 shows the pin location on the board.

Figure 56. Serial Header

Access to the HDMI interface is through the HDMI connector that is located on the bottom side of the board as shown in Figure 57 below.

Figure 57. HDMI Connector

The connector is microHDMI connector. This was done due to the space limitations we had in finding a place to fit the connector. It requires a microHDMI to HDMI cable as shown in Figure 58 below. The cable can be purchased from several different sources.

Figure 58. HDMI Cable

A microSD connector is located on the back or bottom side of the board as shown in Figure 59 below. The microSD card is not supplied with the board.

Figure 59. microSD Connector

When plugging in the SD card, the writing on the card should be up. Align the card with the connector and push to insert. Then release. There should be a click and the card will start to eject slightly, but it then should latch into the connector. To eject the card, push the SD card in and then remove your finger. The SD card will be ejected from the connector.

Do not pull the SD card out or you could damage the connector.

The board comes with a single 10/100 Ethernet interface located next to the power jack as shown in Figure 60.

Figure 60. Ethernet Connector

The PHY supports AutoMDX which means either a straight or a swap cable can be used

A place for an optional 20 pin CTI JTAG header is provided on the board to facilitate the SW development and debugging of the board by using various JTAG emulators. This header is not supplied standard on the board. To use this, a connector will need to be soldered onto the board.

If you need the JTAG connector you can solder it on yourself. No other components are needed. The connector is made by Samtec and the part number is FTR-110-03-G-D-06. You can purchase it from www.digikey.com.

The LCD pins are used on the BeagleBone AI-64 to drive the HDMI framer. These signals are listed in Table 15 below.

Table 15. P8 LCD Conflict Pins

If you are using these pins for other functions, there are a few things to keep in mind:

• On the HDMI Framer, these signals are all inputs so the framer will not be driving these pins.

• The HDMI framer will add a load onto these pins.

• There are small filter caps on these signals which could also change the operation of these pins if used for other functions.

• When used for other functions, the HDMI framer cannot be used.

• There is no way to power off the framer as this would result in the framer being powered through these input pins which would not a be a good idea.

• These pins are also the SYSBOOT pins. DO NOT drive them before theSYS_RESETN signal goes high. If you do, the board may not boot because you would be changing the boot order of the processor.

In order to use these pins, the SW will need to reconfigure them to whatever function you need the pins to do. To keep power low, the HDMI framer should be put in a low power mode via the SW using the I2C0 interface.

Each cape must have its own EEPROM containing information that will allow the SW to identify the board and to configure the expansion headers pins as needed. The one exception is proto boards intended for prototyping. They may or may not have an EEPROM on them. An EEPROM is required for all capes sold in order for them operate correctly when plugged into the BeagleBone AI-64.

The address of the EEPROM will be set via either jumpers or a dipswitch on each expansion board. Figure 61 below is the design of the EEPROM circuit.

The EEPROM used is the same one as is used on the BeagleBone and the BeagleBone AI-64, a CAT24C256. The CAT24C256 is a 256 kb Serial CMOS EEPROM, internally organized as 32,768 words of 8 bits each. It features a 64-byte page write buffer and supports the Standard (100 kHz), Fast (400 kHz) and Fast-Plus (1 MHz) I2C protocol.

Figure 61. Expansion Board EEPROM Without Write Protect

The addressing of this device requires two bytes for the address which is not used on smaller size EEPROMs, which only require only one byte. Other compatible devices may be used as well. Make sure the device you select supports 16 bit addressing. The part package used is at the discretion of the cape designer.