FPGA Design - jhu-cisst/mechatronics-firmware GitHub Wiki

FPGA Design

This page documents the new FPGA architecture, which is a modular design that supports different versions of FPGA board (V1, V2, V3) and different companion boards (QLA, DQLA, DRAC). There is also a BCFG configuration, which corresponds to an FPGA connected to a (yet to be identified) companion board or no board. The basic architecture was introduced in Firmware Rev 8, but further design improvements have been made since that release.

Top Level View

Following is the top-level architecture of the FPGA firmware:

The upper block (FPGA I/O) represents the physical I/O pins in the FPGA design. These I/O are assigned to either the FPGA Comm module (Fw, Eth, Prom) or to the Board module (IO1, IO2). The ID inputs indicate the rotary switch setting (0-F) and are provided to both modules. The FPGA I/O also includes an external clock (CLK, which varies between different FPGA versions) and an LED output. In addition to the external clock (CLK), the Firewire interface also includes clk1394, which is the Firewire clock (49.152 MHz) and is used to generate the sysclk that serves as the primary clock.

The FPGA Comm module encapsulates the functionality associated with the FPGA board (V1, V2, V3). All versions contain a Firewire (Fw) interface. V2 and V3 include Ethernet ports -- one port for V2 and two ports for V3. V1 and V2 include a configuration PROM that stores the FPGA firmware. For V3, this is provided by a MicroSD card on the processor (PS) side of the Zynq, which is not shown.

The Board module implements the functionality provided by the companion board (QLA, DQLA, DRAC). The external I/O is provided via two bi-directional busses, IO1 and IO2. For FPGA V1 and V2, IO1 has 32 signals (IO1[1:32]) and IO2 has 38 signals (IO2[1:38]). For FPGA V3, IO1 has 34 signals (IO1[0:33]) and IO2 has 40 signals (IO2[0:39]).

The CLK and LED signals are generally handled in the top-level module. The CLK signal varies between different FPGA versions:

  • FPGA V1: clk40m (40 MHz)
  • FPGA V2: clk25m (25 MHz)
  • FPGA V3: no external clock (other than clk1394) directly connected to FPGA; uses clocks generated by Zynq processor (PS).

The LED signal drives the LED on the FPGA board, which is separate from the LEDs driven by the Board module. For FPGA V1 and V2, it is connected to the pwr_enable signal (requesting motor power to be enabled). For FPGA V3, it indicates that the 200 MHz clock from the Zynq PS is active.

FPGA Firmware Structure

The above top-level view is implemented for the different board combinations as follows:

Top Level FPGA Comm Board Usage
FPGA1394V1-QLA.v FPGA1394V1.v QLA.v dVRK Controller V1
FPGA1394V2-QLA.v FPGA1394V2.v QLA.v dVRK Controller V2
FPGA1394V3-QLA.v FPGA1394V3.v QLA.v FPGA replacement in V1 or V2 above
FPGA1394V3-DQLA.v FPGA1394V3.v DQLA.v dVRK Controller V3
FPGA1394V3-DRAC.v FPGA1394V3.v DRAC.v dVRK-Si Controller
FPGA1394V3-BCFG.v FPGA1394V3.v BootConfig.v Board detection (or no Board)

FPGA Comm to Board Interface

The following signals are connected between FPGA Comm and Board:

  • Read Bus
    • reg_raddr: 16-bit read address bus, output from FPGA Comm
    • reg_rdata: 32-bit read data bus, output from Board
    • reg_rwait: indicates whether 0 (e.g., register) or 1 (e.g., memory) read wait states, output from Board
    • req_blk_rt_rd: indicates that real-time block read about to start, output from FPGA Comm when it latches timestamp
    • blk_rt_rd: indicates that real-time block read in process, output from FPGA Comm
  • Write Bus
    • reg_waddr: 16-bit write address bus, output from FPGA Comm
    • reg_wdata: 32-bit write data bus, output from FPGA Comm
    • reg_wen: indicates that write data is valid, output from FPGA Comm
    • blk_wstart: indicates start of block write, output from FPGA Comm
    • blk_wen: indicates end of block (or quadlet) write, output from FPGA Comm
  • Timestamp
    • timestamp: 32-bit timestamp, output from Board
  • Watchdog:
    • wdog_timeout: indicates that watchdog has tripped, output from FPGA Comm
    • wdog_clear: signal to reset watchdog, output from Board
    • wdog_period_led: indicates whether LED should display watchdog status, output from FPGA Comm
    • wdog_period_status: watchdog state (3-bit value), output from FPGA Comm

FPGA Comm to FPGA I/O Interface

The following signals are connected between FPGA Comm and FPGA I/O (I/O pins):

  • Firewire (Fw) Interface to TSB41AB2 PHY
    • data: bidirectional 8-bit data bus
    • ctl: bidirectional 2-bit control bus
    • lreq: link request, output from FPGA Comm
    • reset_phy: signal to reset PHY, output from FPGA Comm
  • Ethernet (Eth) Interface
    • FPGA V2: one KSZ8851 MAC/PHY
      • ETH_CSn: PHY chip select, output from FPGA Comm
      • ETH_RSTn: PHY reset, output from FPGA Comm
      • ETH_PME: Power management event (unused), output from FPGA I/O
      • ETH_CMD: Command for PHY register IO, output from FPGA Comm
      • ETH_8n: Indicates whether 8 or 16 bit bus (set to 1, indicating 16-bit bus), output from FPGA Comm
      • ETH_IRQn: Interrupt from PHY, output from FPGA I/O
      • ETH_RDn: Read command to PHY, output from FPGA Comm
      • ETH_WRn: Write command to PHY, output from FPGA Comm
      • SD: Bidirectional 16-bit data bus
    • FPGA V3: two RTL8211F PHY (# is 1 or 2 below)
      • E#_MDIO_C: MDIO clock, output from FPGA Comm
      • E#_MDIO_D: bidirectional MDIO data (directly connected in GMII to RGMII core)
      • E#_RSTn: PHY reset, output from FPGA Comm
      • E#_IRQn: Interrupt from PHY, output from FPGA I/O
      • E#_RxCLK: Receive clock from PHY, output from FPGA I/O
      • E#_RxVAL: Indicates that received data is valid, output from FPGA I/O
      • E#_RxD: 4-bit bidirectional receive data bus, normally output from FPGA I/O, but can be driven by FPGA Comm during PHY reset to reconfigure
      • E#_TxCLK: Transmit clock to PHY, output from FPGA Comm
      • E#_TxEN: Transmit enable to PHY, output from FPGA Comm
      • E#_TxD: 4-bit transmit data bus, output from FPGA Comm
  • Configuration PROM, M25P16 (FPGA V1 and V2)
    • XCCLK: SPI clock, output from FPGA Comm
    • XMISO: SPI data from PROM, output from FPGA I/O
    • XMOSI: SPI data to PROM, output from FPGA Comm
    • XCSn: PROM chip select, output from FPGA Comm
  • Board ID
    • board_id: 4-bit board switch id (0-F), output from FPGA I/O

Board to FPGA I/O Interface

The following signals are connected between Board and FPGA I/O (I/O pins):

  • IO Busses
    • IO1: 32-bit (FPGA V1, V2) or 34-bit (FPGA V3) bidirectional I/O bus
    • IO2: 38-bit (FPGA V1, V2) or 40-bit (FPGA V3) bidirectional I/O bus
  • Board ID
    • board_id: 4-bit board switch id (0-F), output from FPGA I/O