TIPI Hardware Design

TI to Raspberry PI adapter (TIPI) provides the following architectural features:

• 4 CRU output bits
• 32k DSR ROM
• 4 bytes of memmory mapped I/O (2 input and 2 output)

CRU Addressing

The TI-99/4A use TMS9900 CRU to control when peripherals are mapped into the primary CPU memory map. CRU addresses are completely orthogonal to the CPU memory addressing. They are effectively 4096 single bit ports.

TIPI supports CRU address base >1000 thru >1F00. The second nibble of the cru address base can be set by setting the CRUBASE jumper block:

8	4	2	1	CRUBASE	TYPICAL
0	0	0	0	>1000
0	0	0	1	>1100	TI, Corcomp, Myarc FDC
0	0	1	0	>1200
0	0	1	1	>1300	RS232-1/2
0	1	0	0	>1400
0	1	0	1	>1500	RS232-3/4
0	1	1	0	>1600
0	1	1	1	>1700	hexbus
1	0	0	0	>1800
1	0	0	1	>1900
1	0	1	0	>1A00
1	0	1	1	>1B00
1	1	0	0	>1C00
1	1	0	1	>1D00	Triple Tech Clock
1	1	1	0	>1E00	SAMS
1	1	1	1	>1F00	PCode

The following cards have user set CRUBASE:

• Horizon Ramdisk
• IDE
• Mechatronics Gram Karte
• P-Gram

TIPI will use >1100 by default for sideport models to replace the missing function of a TI Floppy Disk controller.

TIPI-PEB models will function best and ship, set to >1000 to allow handling DSK1-3 and DSK device calls before a floppy disk controller.

The TI DSRLNK routine for calling device drivers searches for supporting routines by iterating through the CRUBASE values and searching the linked list headers in each device's DSR ROM. When a matching routine is found, that routine may 'pass' on handling the request. If it does not handle the request and does not alter R11 when returning, then the DSRLNK will continue to search for the next DSR that wishes to handle the request. With this feature, we can have DSR routines to intercept DSK1-3 and DSK. The software configuration can then control if it is handled or if it is passed on to the standard TIFDC (or other device).

For the PEB model, the default CRU base will be >1000.

CRU 'bits'

TIPI uses 4 CRU bits for the following purposes:

CRU No	Function
0	DSR Select
1	RPi Reset
2	DSR ROM A13
3	DSR ROM A14

CRU wire number 0 by TI standards is used to map the DSR ROM for the peripheral into the TMS9900's 0x4000-0x5fff address range. For convenience, we will use this to map the IO ports to the Raspberry PI into the TI memory map as well.

RPi reset signal

RPi reset - CRU bit offset 1 - when held high briefly, and then released low, will cause the primary DSR handing service on the PI to be killed by another tipiwatchdog.service. The operating system then restarts the tipi.service. This happens every time you return to the TI title screen through the execution of the TIPI powerup routine. In this way, unclosed files, sockets, and whatever other resources left allocated are automatically freed.

There is a potentially negative consequence. If you reset the TI without closing a file that you have opened and written to, then the file will not be saved.

DSR Bank Switching

TIPI's current DSR ROM is well within the 8k (minus 8bytes) size limit of the TI memory map. However 32K eproms are used. CRU bits at offset 2 and 3 control the state of the upper address lines of the DSR ROM.

Currently only bank 0 of the 32K EPROM is populated.

Memory Map:

Address	Function
>4000 - >5FF7	DSR ROM
>5FF9	RC
>5FFB	RD
>5FFD	TC
>5FFF	TD

Notice the DSR rom is cut short by 4 words. The IO is mapped to the top end of the DSR ROM address range, so that it is not likely to interfere with the ROM code. Care must be taken to not fill the ROM with required data in the top 4 words, or the data will not be accesssible.

RC is the Raspberry PI Control port. It is an input from the Raspberry PI to the TI. This is used to signal responses to TI requests. Think of this as an ACK port.

RD is the Raspberry PI Data port. It is an input from the Raspberry PI to the TI. This is used to convey a byte of data. If data is offered, it is always made available before the RC port is updated.

TC is the TI Control port. This is an output from the TI, to signal requests for data or signal an offer of data to the Raspberry PI.

TD is the TI Data port. Also an output from the TI.

DSR ROM

The DSR rom contains standard TI headers that allow the TI operating system to lookup the routines that handle the different device names and named functions.

It is a 32K ROM, CRU bits 2 and 3 control switching in 8k banks.

Banking switching the ROM is reserved for future expansion. It is currently not utilized.

Level 3

Level 3 IO is performed with standard Peripheral Access Blocks (PAB) that specify an opcode, file and buffer attributes, and the full device name/path.

opcodes: OPEN, CLOSE, READ, WRITE, LOAD, SAVE, STATUS are supported.

The following 'level 3' File System Management device names are supported:

• TIPI
• DSK0
• DSK1
• DSK2
• DSK3
• DSK4
• DSK
• PI

TIPI refers to the base directory on your Raspberry PI for storing TI-FILES. All storage is underneath TIPI from the host operating system point of view.

DSK1-3 can be mapped. If the mapping does not exist then the DSR will pass control to the next peripheral. The mapping is maintained in the PI.CONFIG special file, so that it can be set by software on the 4A.

DSK.xxxxxxx. will search the directories immediately under TIPI as though they are the TIFDC disk volume names. If no matching directory is found, then the DSR will pass control to the next peripheral.

TP. is the root device for special files only accessible with level 3 IO. Such as TP.DSKMAP for managing legacy drive links.

Level 2

Level 2 IO assumes the pattern of single character 'subroutine' names (like BASIC CALL routines in the DSR, except the names are 1 character and usually not displayable so BASIC won't accidentally call them.)

Level 2 IO is a pattern, not a standard. However to maintain compatibility with any tool that performs file copy, we'll need to implement simulated direct sector IO and direct block IO to the file. Level 2 IO benefits from the same feature that allows the routine to decide to 'pass' on handling it, and cascade to other peripherals. Since we are mapping DSK1-3, we'll use the same level 2 routine names that the TIFDC uses. Use these for "TIPI.", "DSK0." and "DSK4." as well.

This pattern was extended to include directory support.

For a good description of Level 2 IO, see Fred Kaal's Documentation

Not all Level 2 routines make sense for TIPI to implement. The following standard TIFDC routines are NOT implemented:

Subroutine	Function
>10	Direct Sector

The following standard TIFDC routines are implemented:

Subroutine	Function
>12	Protect
>13	File Rename
>14	Direct Input
>15	Direct Output
>16	VDP Buffers
>17	Set Current Path
>18	Create Dir
>19	Delete Dir
>1A	Rename Dir

Alternatively if CRU bit 3 is set, the implemented routines have >30 added to their single character names to match those used by Myarc HFDC harddrives. (experimental or to resolve conflicts... not well tested)