Compensation circuit

See datasheet: https://www.onsemi.com/pub/Collateral/NCP3020-D.PDF

• fp0 = 1 / (2 * pi * sqrt(L * Cout))
  • L = 4.7 uH
  • Cout = 220µF
  • fp0 = 4974Hz = 5kHz
  • (If Cout = 470µF + 22µF + 22µF = 514µF, then fp0 = 3864Hz)
• fz0 = 1 / (2 * pi * ESR * Cout)
  • ESR = 0.042Ω (According to datasheet of https://ch.farnell.com/fr-CH/rubycon/50zl220mefc10x16/condensateur-220-f-50v-20/dp/1144714)
  • fz0 = 17225Hz
• fs = 300 kHz (Switching frequency for the NCP3020A)
• f0 - The main loop zero crossover frequency f0 can be chosen to be 1/10 − 1/5 of the switching frequency
  • Switching frequency: 300 kHz
  • f0 = fs / 6 = 50 kHz

Therefore: fp0 < fz0 < f0 < fs/2, so we choose compensation of Type II, recommended for Electrolytic capacitor.

• Vramp = 1.5V (Ramp−Amplitude Voltage, page 4)

• Gm : 1.4 (Transconductance, page 4)

• Vref: 0.6V

• Rc1 = (2 * pi * f0 * L * Vramp * Vout) / (ESR * Vin * Vref * gm)

Current limit

In NCP3020, the current limit works by comparing:

• The Voltage reference Viref, taken from injecting a 13µA current through the Riset resistor.
• The voltage drop between drain and source of the high side transistor.

We're using a IRLB3813 transistor:

• RDS(on) resistance between drain and source is 1.6mΩ:
• We want to limit the current to 10A.
• Drain to Source voltage drop is: 16mV
• 13µA * Riset = 8mA ==> Riset = 1230Ω

Inductance footprint

According to https://www.pcb-3d.com/tutorials/how-to-calculate-pth-hole-and-pad-diameter-sizes-according-to-ipc-7251-ipc-2222-and-ipc-2221-standards/:

• SBC6-4R7-802
• https://content.kemet.com/datasheets/KEM_L9007_SBC.pdf
• Maximum lead diameter: 1.2mm
• Minumum Hole diameter: Maximum Lead Diameter + 0.25mm (for Level A of IPC-2222) = 1.45 mm
• Pad diameter: Minimum Hole Size + 0.1mm + 0.60mm (for Level A of IPC-2221) = 2.15mm