Usage - janomach/the-hardisc GitHub Wiki

This repository comes with Makefile, containing commands to set up, compile, and simulate a project in the free edition of ModelSim. It contains an example testbench, memory, and interconnect IPs for simulation. The provided testbench automatically loads the memory with the binary data. If the interface protection is enabled, the checksums for individual memory entries are automatically generated and saved in memory. The folder /example contains programs and their binaries that the Hardisc can directly execute in simulation. If you want to change the source tests, you need the RISC-V toolchain. When the toolchain is prepared, you can use the compileTest command in the Makefile to compile the selected tests. Remember to configure the core before simulation.

Set up and compile the Hardisc project:

make hardiscSetup
make hardiscCompile

Simulate the hello_world example with memory latencies:

make hardiscSim BINARY=example/hello_world/test.bin LAT=1

Simulate the matrix example with SEE insertion^1,2 in all groups and logging verbosity 3:

make hardiscSim BINARY=example/matrix/test.bin LOGGING=3 SEE_GROUP=63 SEE_PROB=10

Simulate the hello_world example with SEE insertion¹ only in the predictor's group and with high fault probability:

make hardiscSim BINARY=example/hello_world/test.bin LOGGING=0 SEE_GROUP=4 SEE_PROB=100

Simulate the hello_world example with SEE insertion^1,2 only in the memory group and with high fault probability:

make hardiscSim BINARY=example/hello_world/test.bin LOGGING=0 SEE_GROUP=16 SEE_PROB=100

Simulate the FreeRTOS demo³:

make hardiscSim BINARY=example/freertos/build/RTOSDemo.bin LOGGING=0

Compile the matrix example test:

make compileTest TEST_DIR=example/matrix

1. Do not forget to enable SEE_TESTING in the setting.sv; otherwise, the SEE_PROB will not have an effect.
2. Do not forget to enable PROT_PIPE/PROT_INTF in the setting.sv; otherwise, the core will crash (as is expected without the protection).
3. Check the demo's README file

EXPERIMENT 1: Enable SEE only in the predictor's group and check how the timing changes due to random mispredictions. The protected version of Hardisc is not required in this case, as the SEEs will only be generated in the predictor, and the core can detect any misprediction.

EXPERIMENT 2: Enable the interface protection in the protected pipeline and SEU generation in memory to see how the timing changes due to memory repairs. The example binaries already contain memory repair routines; no compilation is required.