Pipeline overview - janomach/the-hardisc GitHub Wiki

The Hardisc's single-issue in-order pipeline comprises six stages. The first stage (FE) fetches data from an instruction bus into an instruction-fetch buffer (IFB). The second stage (ID) performs instruction alignment and decoding. The alignment is conducted inside the Aligner, which can pop one record out of IFB and output a 16 or 32-bit instruction for the Decoder. The third stage (OP) reads the register file, computes a data bus access address, and checks data hazards. An instruction's intended operation is executed in the fourth stage (EX), which is also leveraged to perform the address phase of the data bus request. The fifth stage (MA) finishes the data phase of the data bus transfer, manages all control transfers to other addresses, and accesses control and status registers (CSR). The sixth stage (WB) is responsible for decoding the data returned from the data bus and writing the results into the register file.

The pipeline stages are instantiated within the top module and are separated by pipeline registers, which prefixes describe which pipeline stage the register separates. For example, a register's prefix is IDOP if it separates the ID and OP stages. The pipeline registers are instantiated in the stage that generates its content. Each pipeline stage is described in a separate file, containing control logic and units used in a particular stage. The load-store unit spans through the EX and MA stages, so it is described in a separate file. The general purpose registers contained in the registers file are also held in a separate module. The RTL description contains parameters and variables defined in the hardisc package.

Reset Point

Most instructions do not require its address to perform the intended operation. The main exceptions are control-transfer instructions, such as branches and jumps. Propagating the address through each pipeline stage and row of IFB would be a waste of area and power. We leverage a mechanism in which the main element is a 32-bit register called a reset point (RP), placed into the MA stage. From a programmer's perspective, it acts as a program counter (PC). The RP is loaded with a boot address during reset. Each finished instruction stores an address of the following instruction in this register. This also implies that whenever the valid instruction is in the MA stage, the RP contains its address. So, each instruction, which needs to know its address, uses the value of RP. Control-transfer instructions write a target address into the RP, and the computational instructions increment the RP by 2 or 4, depending on their width (16- or 32-bit).