Operands prepare - janomach/the-hardisc GitHub Wiki
Overview
The operands prepare (OP) stage prepares source operands for units in the downstream pipeline stages. It reads the register file and checks data hazards between instruction in the OP and instruction in the downstream pipeline stages. A pipeline bubble is inserted if forwarding cannot solve the data hazard. This stage also computes the data bus transfer address to be directly connected to the bus in the next stage.
Registers
| Name | Bit count | Description |
|---|---|---|
| opex_payload | 21 | Instruction payload information |
| opex_op1 | 32 | Operand 1 |
| opex_op2 | 32 | Operand 2 |
| opex_rd | 5 | Destination register address |
| opex_f | 4 | Instruction function information |
| opex_ictrl | 7 | Instruction control indicator |
| opex_fwd | 4 | Forwarding information |
| opex_imiscon | 3 | Instruction misconduct indicator |
Preparer
The preparer checks the sctrl and ictrl data to select the right operands for the next stages. If the instruction is a load or store instruction, it computes the transfer address by adding the immediate value from the payload to the value read from the register file. It checks the data hazard between the instruction in the OP and the instructions in the downstream pipeline stages. If a data hazard is solvable by forwarding in this stage, the data forwarded from the downstream stages is used instead of data read from the register file. If the hazard exists and the forwarding can be done in the EX stage, but the data still needs to be generated, the forwarding information is prepared. A pipeline bubble is inserted if forwarding cannot solve the data hazard. All data hazards not solvable by forwarding are listed here:
- LSU address hazard - Data bus transfer address for load and store instructions is computed in the OP stage. This hazard is present if an instruction generating the base value for the address is currently in the EX stage or the instruction is in the MA stage where its result is generated. Most instructions generate results in the EX stage.
- Data hazard - Present if the EX stage contains instruction, which result is generated in the MA stage (e.g., load, csr, and jal/jalr), but the value is needed by instruction in the OP stage.
- Fix hazard - Present if the OP stage contains a fixed instruction (due to a detected correctable error after the fetch) and the EX or MA stages are not empty.