Memory Access and Write Back - janomach/the-hardisc GitHub Wiki

Overview

The Memory Access (MA) stage performs the data bus transfers' data phase. It also evaluates all conditions (branching, exceptions, interrupts,..) for transferring control to another address. This stage also contains control and status registers (CSR) defined in the privileged RISC-V specification. Due to its simplicity, the Write Back (WB) stage is described in the same file as the MA stage. This stage is only used to write data to the registers file. In the case of a load instruction, the loaded data are modified inside the LSU decoder before writing to the registers file.

Registers

Name	Bit count	Description
mawb_val	32	Result from MA stage
mawb_rd	5	Destination register address
mawb_ictrl	7	Instruction control indicator
mawb_ldinfo	5	Information for decoding of loaded value

Branch unit

This unit signalizes the transfer of control (ToC) to another address for branch and jump instructions. The comparison result of a branch condition is saved in the exma_val[0], while the MSBs of the target address are saved in the exma_val[31:1]. If the prediction for ToC was done in the FE stage, the exma_payload[11] has a value of 1, and the predicted target address is in the BOP. The branch unit signalizes the ToC to the exma_val[31:1]::0 if the branch condition is true and either the prediction was not signalized or was signalized to the wrong address. The ToC to the next address following branch instruction is signalized if the branch condition is false and the prediction was signalized.

CSR Unit

The CSR unit manages control and status registers and evaluates the exception and interrupt conditions. The Hardisc supports only the machine mode from the existing RISC-V privilege modes. The following CSRs are supported:

Name	Address	Description
mstatus	0x300	Machine status register
misa	0x301	ISA and extensions
mie	0x304	Machine interrupt-enable register
mtvec	0x305	Machine trap-handler base address
mepc	0x341	Machine exception program counter
mcause	0x342	Machine trap cause
mtval	0x343	Machine bad address or instruction
mip	0x344	Machine interrupt pending
mscratch	0x340	Scratch register for machine trap handlers
mcycle	0xB00	Machine cycle counter - lower 32 bits
minstret	0xB02	Machine instructions-retired counter - lower 32 bits
mcycleh	0xB80	Machine cycle counter - upper 32 bits
minstreth	0xB82	Machine instructions-retired counter - upper 32 bits
mhartid	0xF14	Hardware thread ID