Instruction Execute - janomach/the-hardisc GitHub Wiki

Overview

The Instruction Execute (EX) stage performs the intended operation for most of the instructions. It uses operands prepared in the OP stage or forwards data from the downstream stages according to the information saved in the opex_fwd. This stage also performs the address phase of the data bus transfers.

Registers

Name	Bit count	Description
exma_payload	12	Instruction payload information
exma_offset	20	Branch/Jump offset information for the Predictor
exma_val	32	Result from EX stage
exma_rd	5	Destination register address
exma_f	4	Instruction function information
exma_ictrl	7	Instruction control indicator
exma_imiscon	3	Instruction misconduct indicator
exma_tstrd	1	Indicator of started transfer

Executor

The Executor unit encloses all computational units and selects the results according to the exma_ictrl.

Arithmetic-Logic Unit

This unit performs base operations with prepared operands for most instructions according to the information saved in the exma_f and exma_ictrl. In the case of branch instructions, this unit also computes the target address parallel to comparing operands.

Multiply-Divide Unit

This unit performs sequential multiplication and division with the prepared operands. The multiplication has a variable-long computation time and lasts between 2 and 18 clock cycles. The division algorithm must still be optimized; it always takes 34 clock cycles to compute the result. A pipeline stall is signalized if the sequential algorithm has not yet finished, which creates a bubble in the MA stage.

Load-Store Unit

The load-store unit (LSU) controls the data bus transfers. The execute stage is leveraged for the address phase of the transfer. If an alignment of the address is not compliant with the intended transfer width (1, 2, or 4 bytes), the transfer is not sent. The data phase is performed in the MA stage. The data, to be sent through the bus, are saved within the LSU while the instruction moves from EX to the MA stage. Even though the transfer address is needed only in the address phase, it is saved into the exma_val for potential exception reporting.