Instruction Decode - janomach/the-hardisc GitHub Wiki
Overview
The instruction decode (ID) stage aligns data from the IFB into RISC-V instructions. The instructions are further decoded and broken into several information chunks for easier processing in the downstream pipeline stages.
Registers
| Name | Bit count | Description |
|---|---|---|
| idop_payload | 21 | Instruction payload information |
| idop_rd | 5 | Destination register address |
| idop_rs1 | 5 | Register source 1 address |
| idop_rs2 | 5 | Register source 2 address |
| idop_f | 4 | Instruction function information |
| idop_sctrl | 4 | Source control indicator |
| idop_ictrl | 7 | Instruction control indicator |
| idop_imiscon | 3 | Instruction misconduct indicator |
Aligner
The core can execute 32-bit (RVI) and 16-bit (RVC) instructions. They are saved in the memory back-to-back, while the core can fetch data only from 4-byte aligned addresses. For example, if a 32-bit instruction at address 0x2 follows a 16-bit instruction at address 0x0, two bus transfers are required (from address 0x0 and 0x4) to compose the RVI instruction. The fetched data are saved in the IFB and then flow through the Aligner, which extracts only one instruction for the Decoder. If the data contains parts of two instructions (e.g., RVC and part of RVI), the Aligner can save the remaining part into the internal registers.
Decoder
The Decoder breaks an instruction from the Aligner into several information chunks for easier processing in the downstream pipeline stages. This includes 5-bit addresses of two source and one destination register and function specifier. The sctrl indicates for the ID stage whether the instruction needs values from the general-purpose registers and whether the source address is zero. The ictrl holds information about the unit selected to process the instruction, the type of instruction (RVI or RVC), and whether the instruction saves results into the general-purpose register. Some registers require immediate value encoded in the instruction. The Decoder extracts this value into the instruction payload signal. The MSB indicates whether there was a prediction from the address of this instruction in the FE stage. Any problem during fetching or decoding is indicated by imiscon.