Dynamic Fault Injection

The RTL description supports dynamic fault injection into all flip-flops of the core to simulate bit-flips. Some wires were also selected to be prone to SEE, including all clocks and reset trees. The testbench supports the injection of transient faults to the bus wires, while the provided memory peripherals can generate bit upsets in the RAMs. The faults are inserted randomly, and the probability is configurable by options. A fault injection condition is evaluated for each bit every clock cycle. Individual resources are grouped, so we can select groups where the fault injection is enabled. The following groups are defined:

0. Core registers (excluding GPR and Predictor)
1. General purpose registers
2. Predictor related registers
3. Selected wires in the core, clock trees, and reset trees
4. Memory
5. Bus wires

The groups can be combined. Individual groups refer to bits in the SEE_GROUP command line options. For example, to enable faults in the Memory and the Core registers, select SEE_GROUP=17. Faults in all groups are enabled with SEE_GROUP=63. The SIMULATION and SEE_TESTING pre-compile time options must be enabled for fault injection.

Static Fault Injection

The repository also contains support for static fault injection. It can be initiated by executing the fault injection script with the target application, for example: ./fi_campaign.sh ../example/matrix/test.bin