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Application

Processors used in harsh environments, where phenomenons like random bit-flips and transient voltage spikes caused by soft errors are concern, require special protection approaches. Lockstep architectures or physical radiation-hardening techniques have protected most processors in such environments. The lockstep protection is straightforward but far from ideal. Connecting two cores to the lockstep requires an external reliable component to detect discrepancies between the cores. Such a system, with area and power overhead >100%, provides only fault detection since selecting a faulty core is impossible. An alternative is a connection of three cores with an external reliable voting component that selects the correct output. Such a system also provides fault tolerance, but the area and power overhead is >200%.

The Hardisc takes a different approach. It integrates the protection into the pipeline, providing fault tolerance with overhead similar to dual-core lockstep. The protection is based on replicating pipeline stages, excluding protecting or replicating the large but not functionality-critical units (e.g., branch predictor). An AMBA 3 AHB-Lite interface of the core is protected against transient faults in the bus. The control signals, driven by the core, are protected by parity bits, whereas the spatial triple redundancy protects response signals from subordinates. The data signals are protected with an error detection/correction code. The protection is separable from the rest of the pipeline, so it is possible to enable/disable these features before simulation/synthesis.

Architecture

The Hardisc has a single-issue in-order pipeline that processes unprivileged 32-bit RISC-V instructions. Apart from the base 32-bit integer instruction set (I), it also implements standard extensions of compressed instructions (C) and multiply and divide (M) instructions. The privileged behavior of the RISC-V core is controlled via Zicsr instructions. Only the Machine mode is supported currently.

Repository

The repository comes with Makefile, containing commands to set up, compile, and simulate a project in the free edition of ModelSim. It contains an example testbench, memory, and interconnect IPs for simulation. The RTL description is designed to support the emulation of random faults in the simulation.

Keep in mind

• The Hardisc is still in development.
• The architecture of the unprotected pipeline has been developed to integrate protection, which means some design approaches were selected with this bias.
• The RTL code style is intentionally chosen to allow fault insertion (e.g., flip-flops in the seu_regs module).
• Power consumption optimizations are yet to be integrated.