PR Summary

Period: 2026-08-16 to 2026-08-29 (Iteration 64) | Total PRs: 37 (37 from Xe2/Xe3/Xe3P) | Lines changed: +42,457 / -11,433

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Triton XPU BE (Xe2/Xe3/Xe3P) (37 PRs, +42,457 / -11,433)

This was a heavy correctness iteration. Two optimization passes that had been silently producing wrong results were repaired, along with a crash affecting flash attention on Battlemage and a bug that made masked loads pick the wrong memory access pattern. In parallel the team built a new signed-arithmetic reasoning capability from the ground up, which lets the compiler turn expensive signed division into cheap unsigned division whenever it can prove the operands are non-negative — a common pattern in PyTorch-generated code. Floating-point 8-bit conversions became both faster and standards-correct for special values. Test infrastructure grew substantially, with SGLang gaining its own dedicated test pipeline and the vLLM tensor-descriptor suite expanding to cover mixture-of-experts kernels. Seven upstream synchronizations were completed, with test pass rates between 99.26% and 99.35%.

Key accomplishments:

• Repaired silent wrong-results bugs in two optimization passes, plus a crash that broke flash attention on Battlemage
• Fixed a performance regression in grouped matrix multiplication caused by an earlier masked-load change, while keeping that change's large gain on the batched variant
• Delivered a new signed-arithmetic reasoning capability that converts costly signed division into unsigned division under a runtime check, targeting PyTorch-generated code
• Made 8-bit floating-point conversion roughly three times cheaper and corrected its handling of infinity and not-a-number values
• Curbed excessive just-in-time recompilation from tensor descriptors, which previously created a new kernel variant for every distinct tensor shape
• Gave SGLang its own test pipeline with per-kernel-family suites on both Ponte Vecchio and Battlemage
• Restored event-less kernel submission, reducing per-launch overhead

Memory Access & Lowering

2D block I/O tile geometry and eligibility, tensor descriptor specialization limits, and 8-bit float conversion sequences.

• #7848 Decline block IO when the mask degenerates the 2D block tile — Clamps each tile dimension to the mask's constancy, fixing the gemm-grouped regression from #7205 (5.56→1.27 TFlops) while keeping its gemm-grouped-batched gain. (+100/-0, @whitneywhtsang)
• #7842 Declare predicated load as reading only argument memory — Adds the missing memory(...) clause so LLVM and IGC can hoist, reorder and CSE __spirv_PredicatedLoadINTEL instead of assuming it writes all memory. (+16/-3, @whitneywhtsang)
• #7803 Fix 1D reshape block I/O tile geometry for W > threadsPerWarp — Routes the 1D→2D reshape paths through the shared getBlockIOTileSize helper, fixing silently wrong data when the width exceeds the warp thread count; addresses #6578. (+341/-111, @NathanVoldman)
• #7797 Cap shape divisibility specialization at 4 — Bounds host tensor descriptor divisibility specialization at 4, the highest divisor any element type actually needs. (+46/-19, @whitneywhtsang)
• #7793 Use max divisibility for bounded specialization — Encodes maximum power-of-2 shape divisibility instead of exact shape values, ending unbounded JIT specialization; fixes #7691. (+258/-55, @whitneywhtsang)
• #7775 Rewrite fp8e4m3 -> fp16 with oneDNN sequence — Replaces a ~20-op converter with oneDNN's 6-op sequence, using IEEE Inf * 0 = NaN to fold the NaN fixup into the rebias. (+182/-101, @etiotto)
• #7772 Propagate Inf/NaN in fp8e4m3 / fp8e5m2 -> bf16 conversion — Reserved fp8 encodings decoded to finite values (e.g. ±480.0) instead of NaN/Inf; both bf16 paths fixed with sign preserved. (+170/-52, @etiotto)

Correctness Fixes

Silent miscompiles, crashes, and unsound transformations found and fixed across the pass pipeline.

• #7841 tl.dot: rejected small N/small K DPAS shapes fall back to FMA — Replaces the hard minimum dot-size error with a blocked-layout FMA fallback, fixing the OLMoE LoRA fixture failure in #7602. (+99/-24, @sarah12121212)
• #7853 Disable SPV_INTEL_int4 extension — Drops the experimental xe3p+ extension added in #7454, which broke vLLM's mamba tests. (+1/-20, @dev-tomek)
• #7801 Read the core clock rate from the target properties only — Removes a driver.active fallback from parse_target(), which must stay driver-free since it runs on every compile. (+1/-8, @wdziurdz)
• #7844 Fix dominance violation on multi-loop kernels — ReduceVariableLiveness::moveOperand() rewired all users with an unconditional RAUW, pointing pre-loop users at a non-dominating definition; broke causal flash attention on BMG. (+129/-6, @etiotto)
• #7791 Fix crashes and unsound mask drops — Fixes six defects in TritonIntelRemoveMasks: null RAUW, null cast on dynamic bounds, double scf.yield, and unsound mask drops; fixes #7790. (+447/-43, @etiotto)
• #7756 Fix arith.bitcast on multi-element tensors in LLVM lowering — Emits per-element scalar bitcasts instead of one llvm.bitcast on an aggregate struct, which the verifier rejects. (+76/-0, @NathanVoldman)
• #7751 Fix silent miscompiles, crash, and dropped loop attributes — Rebuilds LoopDistribute on mlir::getBackwardSlice with explicit op classification, fixing frozen iter_args, silent deletion of unrecognized pure ops, a nested-region capture crash, and dropped loop attributes. (+1214/-38, @etiotto)
• #7752 Clamp remainder divisibility to the result contiguity — RemOpAxisInfoVisitor claimed divisibility valid only for the first element of a dividend group as if it held for result groups. (+49/-1, @whitneywhtsang)

Signed Arithmetic & Compiler Optimization

A new goal-directed signedness prover and the passes that consume it, plus layout-conversion and loop-distribution cost improvements.

• #7847 Leverage range analysis in SimplifySignedArithmetic — Queries IntegerRangeAnalysis first when testing non-negativity or strict positivity. (+175/-2, @whitneywhtsang)
• #7786 Price sub-group-shuffle converts at register rate — getConvertCost charged every convert the SLM round-trip rate; shuffles never touch shared memory, so they are now priced at register rate and the cost function is memoized. Extends #7685. (+228/-44, @etiotto)
• #7804 Allow carried chains that depend on a single accumulator — Gives each iter_arg slot an owner so a chain reading exactly one accumulator is computed in that accumulator's loop; closes #7784. (+731/-127, @etiotto)
• #7822 Speculate signed div/rem into unsigned under a runtime assertion — New TTIR pass rewriting arith.divsi/arith.remsi to unsigned form guarded by a runtime non-negativity assertion. (+832/-0, @whitneywhtsang)
• #7807 Add SignednessProver analysis — Goal-directed prover that answers "what would make this value non-negative", decomposing operations when range analysis is inconclusive. (+914/-0, @whitneywhtsang)
• #7808 Add SignedDivRemDeduction utility — Mirrors the AxisInfo conditions to identify signed div/rem sites where deductions would apply if the dividend were proven non-negative. (+272/-0, @whitneywhtsang)

Runtime & Developer Tooling

Kernel submission overhead and script portability.

• #7865 Use uv pip when pip is not available — Adds a sourced scripts/pip-utils.sh wrapper so scripts work in uv venv environments without breaking traditional tooling. (+101/-17, @gshimansky)
• #7823 Add DLE_VERSION capture and output to capture-hw-details.sh — Records the DLE version alongside the other driver and hardware details. (+7/-0, @exolyr)
• #7670 Re-land event-less kernel submission — Re-lands #6361 (reverted in #7598) using syclex::submit, gated off the LTS driver line where device asserts and prints need a host event wait. (+104/-23, @mieshkiwrk)

Upstream Alignment

7 upstream merges from OpenAI Triton (commits faa8c28, 800558f, 63068fc, 1d2da15, 4313a23, 040039b, 0699c93) — pass rate 99.26–99.35%.

Test & CI Reliability

New SGLang test pipeline, vLLM tensor-descriptor suite expansion, platform selection, and Windows build split.

• #7622 Update PyTorch pin — Advances the PyTorch pin. (+10/-5, @anmyachev)
• #7725 Standalone SGLang test workflow with per-family suites on PVC and BMG — Gives SGLang its own reusable CI workflow mirroring vLLM: one wheel build, matrix suites split by kernel family (attention, quant, moe, mamba, gdn), pass-rate reporting, and BMG support. (+855/-65, @dev-tomek)
• #7851 Add UT for issue #7491 — Adds a unit test covering #7491. (+18/-0, @anmyachev)
• #7744 Add fused_moe tests to the vllm-tdesc test-suite — Extends the tensor-descriptor suite to fused_moe and reorganizes the vllm_moe tests; closes #7743. (+422/-5, @quinnlp)
• #7835 Report environment details before benchmarks — Records Agama/IGC/Level Zero, GPU device and torch versions into the benchmark-reports artifact, motivated by an Agama 39122.14 regression. (+18/-0, @quinnlp)
• #7776 Update MoE kernel grid to use autotune-selected BLOCK_M and BLOCK_N — The batched MoE launch grid used vLLM's config values rather than the autotuner's, launching too few programs and causing accuracy failures. (+6/-16, @sarah12121212)
• #7825 Add platform selection logic to on-label workflow — Introduces bmg-only/pvc-only labels and a select-benchmark-platforms job; PVC benchmarks temporarily disabled by default due to machine availability. (+49/-11, @whitneywhtsang)
• #7810 Fix on-label workflow canceling runs when multiple benchmark labels are added — Two benchmark labels produced two workflow runs sharing one concurrency group, so the second cancelled the first. (+12/-12, @whitneywhtsang)
• #7769 Add PR path change triggers to vLLM test workflows — Runs vLLM tests automatically when relevant paths change; closes #7783. (+18/-2, @quinnlp)
• #7766 Update vLLM pin to 017e9f4 — Fixes gdn_attn test failures with no benchmark performance impact on b580; closes #7767 and #7705. (+63/-32, @quinnlp)
• #7630 Split Windows build — Splits the Triton build step so it can run on any Windows machine rather than requiring a GPU runner; part of #7443. (+113/-20, @kwasd)
• #7741 Add batched_moe tests to the vllm-tdesc test-suite — The suite now applies all enabled kernel patches; batched_moe needs VLLM_TRITON_USE_TD set. Closes #7742. (+79/-21, @quinnlp)