1D to 2D Block IO Reshape Optimization - intel/intel-xpu-backend-for-triton GitHub Wiki
1D Strided Access → 2D Block I/O Reshape Optimization
Overview
This presentation explains the 1D-to-2D Block I/O Reshape optimization added to the Intel XPU Backend for Triton in the MaterializeBlockPointer pass.
The optimization detects flattened 1D gather/scatter patterns produced by PyTorch Inductor (offset = idx % W + idx / W * S) and reshapes them into efficient 2D block load/store instructions, achieving 80%+ bandwidth improvement on PVC.
Download
1d-reshape-optimization.pptx (4 slides + speaker notes)
Slides Summary
| # | Title | Key Point |
|---|---|---|
| 1 | The Problem | Inductor flattens 2D tiles into 1D scatter/gather → N LSC messages |
| 2 | The Solution | Pattern match W/H/S, reshape to 2D, emit single block I/O instruction |
| 3 | Load vs Store | Loads need ConvertLayoutOp (HW delivery order mismatch); stores don't |
| 4 | Timeline & Results | 5 PRs over 2 weeks; +81% avg bandwidth on PVC |
Related
- Issue #6532 — Motivating issue
- PR #6531 — Initial store reshape
- PR #6693 — Load reshape (this presentation)
- Source:
third_party/intel/lib/TritonIntelGPUTransforms/MaterializeBlockPointer.cpp