This protocol is based on the original protocol1 from openHPSDR consisting of USB_protocol_V document and Metis. It is intended to remain compatible with a core subset of the openHPSDR protocol such that the Hermes-Lite2 may operate in basic mode with standard openHPSDR software.

The Hermes-Lite2 will use Board_ID 0x07.

Command & Control	Bits	Description
C0	[7]
	[6:1]	ADDR[5:0]
	[0]	MOX (1 = active, 0 = inactive)
C1	[7:0]	DATA[31:24]
C2	[7:0]	DATA[23:16]
C3	[7:0]	DATA[15:8]
C4	[7:0]	DATA[7:0]

This table shows the Hermes-Lite2 64 word memory map. These 64 addresses correspond to the first 64 addresses of the original openHPSDR's 128 address space. Since only 17 addresses are currently in use by the original openHPSDR protocol, no existing funtionality is left uncovered. Instead of the full address space, Hermes-Lite2 repurposes C0[7] to serve as a request bit, RQST. If this bit is set, the Hermes-Lite2 will respond as described later. If this bit is not set, the Hermes-Lite2 will cycle through the standard openHPSDR responses as specified in the original protocol.

Please refer to the original openHPSDR protocol when adding or repurposing locations. As of version 1.58, openHPSDR defines uses for addresses from 0x00 up to and including 0x11.

ADDR	DATA	Description
0x00	[25:24]	Speed (00=48kHz, 01=96kHz, 10=192kHz, 11=384kHz)
0x00	[23:17]	Open Collector Outputs on Penelope or Hermes
0x00	[12]	Hardware AGC (0=off, 1=on)
0x00	[10]	VNA fixed RX Gain (0=-6dB, 1=+6dB)
0x00	[6:3]	Number of Receivers (0000=1 to max 1011=12)
0x00	[2]	Duplex (0=off, 1=on)
0x01	[31:0]	TX1 NCO Frequency in Hz
0x02	[31:0]	RX1 NCO Frequency in Hz
0x03	[31:0]	If present, RX2 NCO Frequency in Hz
0x04	[31:0]	If present, RX3 NCO Frequency in Hz
0x05	[31:0]	If present, RX4 NCO Frequency in Hz
0x06	[31:0]	If present, RX5 NCO Frequency in Hz
0x07	[31:0]	If present, RX6 NCO Frequency in Hz
0x08	[31:0]	If present, RX7 NCO Frequency in Hz
0x09	[31:24]	Hermes TX Drive Level
0x09	[23]	VNA mode (0=off, 1=on)
0x09	[22]	Alex manual mode (0=off, 1=on) (Not implemented yet)
0x09	[19]	Onboard PA (0=off, 1=on)
0x09	[18]	Q5 switch external PTT in low power mode
0x09	[15:8]	I2C RX filter (Not implemented), or VNA count MSB
0x09	[7:0]	I2C TX filter (Not implemented), or VNA count LSB
0x0a	[22]	PureSignal (0=disable, 1=enable)
0x0a	[6]	See LNA gain section below
0x0a	[5:0]	LNA[5:0] gain
0x12	[31:0]	If present, RX8 NCO Frequency in Hz
0x13	[31:0]	If present, RX9 NCO Frequency in Hz
0x14	[31:0]	If present, RX10 NCO Frequency in Hz
0x15	[31:0]	If present, RX11 NCO Frequency in Hz
0x16	[31:0]	If present, RX12 NCO Frequency in Hz
0x2b	[31:24]	Predistortion subindex
0x2b	[19:16]	Predistortion
0x3b	[31:24]	AD9866 SPI cookie, must be 0x06 to write
0x3b	[20:16]	AD9866 SPI address
0x3b	[7:0]	AD9866 SPI data
0x3c	[31:24]	I2C1 cookie, must be 0x06 to write
0x3c	[23]	I2C1 stop at end (0=continue, 1=stop)
0x3c	[22:16]	I2C1 target chip address
0x3c	[15:8]	I2C1 control
0x3c	[7:0]	I2C1 data
0x3d	[31:24]	I2C2 cookie, must be 0x06 to write
0x3d	[23]	I2C2 stop at end (0=continue, 1=stop)
0x3d	[22:16]	I2C2 target chip address
0x3d	[15:8]	I2C2 control
0x3d	[7:0]	I2C2 data
0x3f	[31:0]	Extended Write Data

When bit 6 at address 0x0a is set, then LNA LNA[5:0] is passed directly to the AD9866 for full -12dB (0) to +48dB (60) gain range. When bit 6 is not set, Hermes backwards compatibility is selected. Only gain levels from -12dB to +20dB are available. The value LNA[4:0] is 32 bits of attenuation to match the Hermes, where 0 is no attenuation (+19dB) and 32 is maximum attenuation (-12dB). The Hermes has +20dB of gain by default which is attenuated by the step attenuator. Address 0x0a bit 5 selects whether the step attenuator is on (1) or off (0). If the step attenuator is off, the Hermes-Lite will default to +20dB of LNA gain.

Since the Hermes-Lite2 does not include an audio codec, there is no use for the audio data sent to the Hermes-Lite2. The first stereo audio sample pair, , as described in the openHPSDR specification, occurs immediately after the 32-bit DATA word in a frame. This 32-bit word is reserved for Hermes-Lite2 use as follows:

• [31:24] Reserved
• [15:0] EADDR

The extended address, EADDR, is the location to which the extended write data, base address 0x3f, will be written. This reserves space for possible future expansion. The extended address space does not overlap with the base address space. The extended memory map will be added as needed.

The Hermes-Lite 2 uses I2C to communicate with a companion filter board. Software can always use the low-level I2C interface and write any desired I2C command to a custom companion filter board. To support some integration with PowerSDR and other software, the Hermes-Lite 2 will also translate some protocol 1 filter selection commands into appropriate I2C commands for an attached MCP23008 I2C to 8-bit parallel port bus expander at address 0x20.

Standard mode is enabled when Alex manual mode enabled is off, the default. See the memory map above to identify the Alex manual mode enabled bit. In this mode, the gateware sends the 7 bits of "Open Collector Outputs on Penelope or Hermes" as specified in the above memory map. These 7 bits map to bits GP6:GP0 on the MCP23008. These bits stay the same during TX and RX. These bits are only updated when software sends a new "Open Collector Outputs on Penelope or Hermes" value. The MCP23008 GP7 will be 1 during transmit, 0 during receive. (GP7 is not yet implemented.)

When Alex manual mode is enabled, Alex HPF, LPF and various other Alex control bits are repurposed to create an 8-bit TX and another 8-bit RX filter selection setting. See "I2C Filter setting selection" in the above memory map. The 8-bit RX setting is sent to the MCP23008 as GP7:GP0 during RX, and the 8-bit TX setting is sent during TX. It is up to software and the companion filter board to define a meaning for each bit. Some example are described below.

If a user wants bit 7 to indicate TX or RX, bit 7 must be set in the TX setting and cleared in the RX setting.

If a user wants both HPF and LPF selection (instead of one hot filter selection), then a user can define bits 6:4 as a 1 of 8 HPF selection and bits 3:0 as a 1 of 16 LPF selection.

Bias voltages are set via I2C2. Bias[7:0] is an 8-bit value. A value of 0xff is the lowest bias voltage in the range. A value of 0x00 is the highest. There are 256 linear steps. The actual bias range depends on the PA implemented.

During experimentation or initial current measurement, set the volatile value. Once a user picks a final bias value, set the nonvolatile value. The nonvolatile value is only loaded at the next power cycle.

I2C2 = 0x06a800vv where vv is bias0[7:0]

I2C2 = 0x06a820vv where vv is bias0[7:0]

I2C2 = 0x06a810vv where vv is bias1[7:0]

I2C2 = 0x06a830vv where vv is bias1[7:0]

C0[7] is the ACK flag. It is set if this response from the Hermes-Lite2 is due to receiving a RQST from the PC. The remaining bits of C0 are decoded differently depending on the state of C0[7].

Command & Control	Bits	Description
C0	[7]	ACK==0
	[6:3]	RADDR[3:0]
	[2]	Dot
	[1]	Dash
	[0]	PTT
C1	[7:0]	RDATA[31:24]
C2	[7:0]	RDATA[23:16]
C3	[7:0]	RDATA[15:8]
C4	[7:0]	RDATA[7:0]

Only the first 3 addresses are in use and correspond to response in the original protocol.

RADDR	RDATA	Description
0x00	[24]	RF ADC Overload
0x00	[7:0]	Firmware Version
0x01	[31:16]	Temperature
0x01	[15:0]	Forward Power
0x02	[31:16]	Reverse Power
0x02	[15:0]	Current

Command & Control	Bits	Description
C0	[7]	ACK==1
	[6:1]	RADDR[5:0]
	[0]	PTT
C1	[7:0]	RDATA[31:24]
C2	[7:0]	RDATA[23:16]
C3	[7:0]	RDATA[15:8]
C4	[7:0]	RDATA[7:0]

By default, gateware will echo the request address and data, RADDR=ADDR and RDATA=DATA, once per each request received. Future requests may respond with specific data and will be defined here when needed. Note that historic commands such as set RX frequency are forced to respond if RQST was set.

To prevent starvation of the classic responses, software should only send a command with RQST set periodically. For example, every other sent command may be one that is a request.