code:backup - ikarishinjieva/unixV6-code-analyze-chs GitHub Wiki
1007
1008 /* ------------------------- */
1009 .globl _backup
1010 /* ------------------------- */
1011 .globl _regloc
1012 _backup:
1014 mov r2,-(sp)
1015 jsr pc,backup
1017 mov (sp)+,r2
1018 movb jflg,r0
1019 bne 2f
1020 mov 2(sp),r0
1022 jsr pc,1f
1024 jsr pc,1f
1025 movb _regloc+7,r1
1026 asl r1
1027 add r0,r1
1029 clr r0
1030 2:
1031 rts pc
1032 1:
1033 mov r1,-(sp)
1034 asr (sp)
1035 asr (sp)
1036 asr (sp)
1037 bic $!7,r1
1038 movb _regloc(r1),r1
1039 asl r1
1040 add r0,r1
1041 sub (sp)+,(r1)
1042 rts pc
1043
1044 / hard part
1045 / simulate the ssr2 register missing on 11/40
1046
1047 backup:
1048 clr r2/ backup register ssr1
1049 mov $1,bflg/ clrs jflg
1051 jsr pc,fetch
1052 mov r0,r1
1053 ash $-11.,r0
1054 bic $!36,r0
1055 jmp *0f(r0)
1056 0: t00; t01; t02; t03; t04; t05; t06; t07
1057 t10; t11; t12; t13; t14; t15; t16; t17
1058
1059 t00:
1060 clrb bflg
1061
1062 t10:
1063 mov r1,r0
1064 swab r0
1065 bic $!16,r0
1066 jmp *0f(r0)
1067 0: u0; u1; u2; u3; u4; u5; u6; u7
1068
1069 u6: / single op, m[tf]pi, sxt, illegal
1070 bit $400,r1
1071 beq u5/ all but m[tf], sxt
1072 bit $200,r1
1074 bit $100,r1
1076
1077 / simulate mtpi with double (sp)+,dd
1078 bic $4000,r1/ turn instr into (sp)+
1079 br t01
1080
1081 / simulate mfpi with double ss,-(sp)
1082 1:
1083 ash $6,r1
1084 bis $46,r1/ -(sp)
1085 br t01
1086
1087 u4: / jsr
1088 mov r1,r0
1089 jsr pc,setreg / assume no fault
1090 bis $173000,r2 / -2 from sp
1091 rts pc
1092
1093 t07: / EIS
1094 clrb bflg
1095
1100
1101 t01: / mov
1102 t02: / cmp
1103 t03: / bit
1104 t04: / bic
1105 t05: / bis
1106 t06: / add
1107 t16: / sub
1108 clrb bflg
1109
1110 t11: / movb
1111 t12: / cmpb
1112 t13: / bitb
1113 t14: / bicb
1114 t15: / bisb
1115 mov r1,r0
1116 ash $-6,r0
1117 jsr pc,setreg
1118 swab r2
1119 mov r1,r0
1120 jsr pc,setreg
1121
1122 / if delta(dest) is zero,
1123 / no need to fetch source
1124
1125 bit $370,r2
1126 beq 1f
1127
1128 / if mode(source) is R,
1129 / no fault is possible
1130
1131 bit $7000,r1
1132 beq 1f
1133
1134 / if reg(source) is reg(dest),
1135 / too bad.
1136
1137 mov r2,-(sp)
1138 bic $174370,(sp)
1139 cmpb 1(sp),(sp)+
1140 beq t17
1141
1142 / start source cycle
1143 / pick up value of reg
1144
1145 mov r1,r0
1146 ash $-6,r0
1147 bic $!7,r0
1148 movb _regloc(r0),r0
1149 asl r0
1151 mov (r0),r0
1152
1153 / if reg has been incremented,
1154 / must decrement it before fetch
1155
1156 bit $174000,r2
1157 ble 2f
1158 dec r0
1159 bit $10000,r2
1160 beq 2f
1161 dec r0
1162 2:
1163
1164 / if mode is 6,7 fetch and add X(R) to R
1165
1166 bit $4000,r1
1167 beq 2f
1168 bit $2000,r1
1169 beq 2f
1170 mov r0,-(sp)
1172 sdd $2,r0
1173 jsr pc,fetch
1174 add (sp)+,r0
1175 2:
1176
1177 / fetch operand
1178 / if mode is 3,5,7 fetch *
1179
1180 jsr pc,fetch
1181 bit $1000,r1
1182 beq 1f
1183 bit $6000,r1
1184 bne fetch
1185 1:
1186 rts pc
1187
1188 t17: / illegal
1189 u1: / br
1190 u2: / br
1191 u3: / br
1192 u7: / illegal
1193 incb jflg
1194 rts pc
1195
1196 setreg:
1197 mov r0,-(sp)
1198 bic $!7,r0
1199 bis r0,r2
1200 mov (sp)+,r0
1201 ash $-3,r0
1202 bic $!7,r0
1203 movb 0f(r0),r0
1204 tstb bflg
1205 beq 1f
1206 bit $2,r2
1207 beq 2f
1208 bit $4,r2
1209 beq 2f
1210 1:
1211 cmp r0,$20
1212 beq 2f
1213 cmp r0,$-20
1214 beq 2f
1215 asl r0
1216 2:
1217 bisb r0,r2
1218 rts pc
1219
1220 0: .byte 0,0,10,20,-10,-20,0,0
1221
1222 fetch:
1223 bic $1,r0
1224 mov nofault,-(sp)
1225 mov $1f,nofault
1226 mfpi (r0)
1227 mov (sp)+,r0
1228 mov (sp)+,nofault
1229 rts pc
1230
1231 1:
1232 mov (sp)+,nofault
1233 clrb r2 / clear out dest on fault
1234 mov $-1,r0
1235 rts pc
1236
1237 .bss
1238 bflg: .=.+1
1239 jflg: .=.+1
1240 .text
1241