Control Registers - hdl4fpga/hdl4fpga GitHub Wiki

Control register input system

Control registers are set through the serial input interface. Data sent is composed by a stream of packets of bits. The first field has a size of 8 bits and states the register ID which data is sent to, the second field tells the length of the data. The length has to be decrease by one previous to be sent, e.g : a 0 on that field indicates 8 bits of data, i.e. : at least 8 bits of data should be sent. The third field is the data to be written into the register. A stream of those packets can be sent one after the other to set as many register as it is desired.

	Register ID	Length	Data
	Register ID	Length	Data
Size	8 bits	8 bits	( Length +1) x 8 bits

Control register map

source : https://github.com/hdl4fpga/hdl4fpga/blob/56f8850b2e3ff8def2a52b6d14c7ce70beb13195/library/scope/scopeiopkg.vhd#L475

Name	ID	bit fields
Horizontal Axis	0x10	scale	4	offset	16
Palette	0x11	color	24	id	7
Trigger	0x12	chanid	6	level	9	edge	1	ena	1
Gain	0x13	chanid	6	gainid	4
Vertical Axis	0x14	chanid	6	offset	13
Pointer	0x15	pointery	11	pointery	11
DMA Base Address	0x16	address	32
DMA Transfer Length	0x17	length	32	number of word to transfer
DMA FIFO buffer	0x18	data	Maximum of 256 of eigth-bits bytes

DMA Base Address

It holds the DDR controller word address. That is, the DDR controller word data can be different from DRAM IC. This always happens on DDR DRAM ICs. On SDR SDRAM, if the base clock for the controller and the SDRAM is the same, the word size should be the same. When this register is written, the FIFO is set to empty. It should be the first register to be sent to set the DMA transfer.

DMA Transfer Length

It holds the transfer length and starts the DMA transfer. The value should be the number of words to transfer minus one. When it's received, it starts the DMA transfer. It should be the last register to be written to complete the transfer.

DMA FIFO buffer

It stores the data to be transferred to the DRAM. Once the DMA Base Address is set, data can be sent to the FIFO buffer. The unit here is eight-bits bytes. DMA Transfer length should comply the data that have been sent to the FIFO. Multiple transfers can be sent to fill the FIFO.

Example

DRAM controller word size : 16 bits

DMA Base word Address : 0x00000000

DMA Transfer length : 130 words

Send the base address and set the FIFO empty

0x16 0x03 0x00 0x00 0x00 0x00

Fill the FIFO

Transfer length is 130 words, so FIFO should be filled with one transfer of 256 eight-bits bytes transfer and another transfer of 4 eight-bits bytes.

0x18	0xff	0x ... 0x
0x18	0x03	0x 0x 0x 0x

Send the DMA Transfer length and start the transfer.

0x17 0x03 0x00 0x00 0x00 0x81