FPGA PLL - hampussandberg/HexConnect GitHub Wiki

On the board there is a 50 MHz oscillator but inside we would like to use a higher frequency of 100 MHz. This is done by using one of the two available PLLs inside the Cyclone IV E FPGA.

SDRAM Clock

Feeding output of PLL to an output pin

Page 83 (5-21) in Cyclone IV Handbook

Clock Feedback Modes

Page 85 (5-23) in Cyclone IV Handbook

Warning: PLL "pll:pll|altpll:altpll_component|pll_altpll1:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins