FPGA Monitor - hampussandberg/HexConnect GitHub Wiki

Introduction

I have learned during my time developing the HDL code for the data processor that debugging the code running on the FPGA can be hard but often needed. You can (and should) of course simulate the HDL code beforehand on the computer in order to detect any major design errors but sometimes the errors don't show up until it is running on the hardware.

There are different resources available that can do this kind of probing needed, for example the SignalTap from Altera. I have had a look at it and it does seem promising but also complex which means it would take some time to get used to. Altera offer a free training course that I will do at some point.

As an alternative I have decided to create a simple FPGA monitor which can be used to view various register values and also set them via a UART interface. This is the content of this page.