CCirc MLIR Dialect - gt-tinker/qwerty GitHub Wiki

CCirc MLIR Dialect Spec

This document describes our CCirc MLIR dialect aimed to replace mockturtle's XAG.

Types

There are three type:

  • WireType: A one-bit wire
  • WireBundleType: (Jaehun, refer to BitBundle in the Qwerty dialect)
    • Has a uint64_t parameter called dim
  • CircuitType: The type of a Circuit op (see below)
    • Has two uint64_t parameters, in_dim and out_dim

We choose not to use the existing i1 type in MLIR because a circuit wire should not be usable as an scf.if condition or an operand to an arith op.

Ops

Logical Ops

  • AndOp: Bitwise AND

    • Inputs:
      1. left (of type Wire)
      2. right (of type Wire)
    • Output:
      1. result (of type Wire)

  • OrOp: Bitwise OR

    • Inputs:
      1. left (of type Wire)
      2. right (of type Wire)
    • Output:
      1. result (of type Wire)

  • XorOp: Bitwise XOR

    • Inputs:
      1. left (of type Wire)
      2. right (of type Wire)
    • Output:
      1. result (of type Wire)

  • NotOp: Bitwise NOT (Jaehun, this is a good one to start with)

    • Inputs:
      1. operand (of type Wire)
    • Output:
      1. result (of type Wire)

Bitwise Ops

  • RotrOp: Right bit rotation

    • Inputs:
      1. val (of type WireBundle)
      2. amt (of type WireBundle)
    • Output:
      1. result (of type WireBundle)
    • Verification: val and result should have the same type.

  • RotlOp: Left bit rotation

    • Inputs:
      1. val (of type WireBundle)
      2. amt (of type WireBundle)
    • Output:
      1. result (of type WireBundle)
    • Verification: val and result should have the same type.

Structural Ops

  • WireBundlePackOp: Create a WireBundle from Wires (Jaehun, refer to the BitBundlePackOp in the Qwerty dialect)

    • Inputs:
      1. wires (of type Variadic<Wire>)
    • Output:
      1. bundle (of type WireBundle)

  • WireBundleUnpackOp: Unpack a WireBundle into Wires (Jaehun, refer to the BitBundleUnpackOp in the Qwerty dialect)

    • Inputs:
      1. bundle (of type WireBundle)
    • Output:
      1. wires (of type Variadic<Wire>)

  • CircuitOp: A top-level circuit with inputs and outputs (Jaehun, I will handle this one and model it after the FuncOp in the Qwerty dialect)

    • Traits: IsolatedFromAbove, Callable
    • Interfaces: CallableOpInterface, FunctionOpInterface
    • Attributes: symbol name, symbol visiblity, and a CircuitType type
    • Regions: One-block body. Block has one argument (a WireBundle) and yields one value (a WireBundle)
    • Verifier: Checks that the body only contains ops from this dialect and that the function type is from WireBundle to WireBundle
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