CAN Bus timing, minimal example on SAMe54 Xplained Pro - gneidermeier/CANFDDemo_SAMe54_START GitHub Wiki
This guide will demonstrate a minimal software project to use the CAN module on SAMe54 Xplained Pro.
Generating and importing starter project into Atmel Studio
- Open Atmel START web based graphical configuration tool and click BROWSE EXAMPLES
- Filter by Category: (e.g. I/O) and/or Board: (e.g. SAM E54 Xplained Pro)
- Select LED flasher and click Download Selected Example
- In Atmel Studio, [File | Import | Atmel Start Project] and select the downloaded project bundle LED flasher.atzip
- Build (F7) and Debug (F5)
This demonstration will illustrate a minimal configuration of the CAN bus timing registers to achieve a CAN bus rate of 500 kb/s. The SAMe54 CAN module must be clocked by a generic clock (GCLK). The LED Flasher example project as imported, has CPU clocked from the external oscillator (XOSC1) at 12 MHz. The GCLK instance can also be configured to use XOSC1 as well.
Add CAN driver software component
- In Atmel START, switch to DASHBOARD tab, click Add software component
- In ADD SOFTWARE COMPONENTS dialog, expand Drivers, select CAN and click Add component(s)
- Click the gear icon on CAN_0 component
- Under CLOCKS set CAN to Generic clock generator 0
- Under COMPONENT SIGNALS set RX and TX to pins PB13 & PB12 respectively
- Driver Instance should indicate CAN1
On the DASHBOARD tab, scroll down to find the configuration for CAN_0 peripheral - look for the section BASIC CONFIGURATION
- uncheck FD Enable and BR Enable if they are checked
- ignore Data Quality of Service (defines the memory priority access during the Message RAM read/write data operation)
In the CAN_0 configuration, look for the section NORMAL BIT TIMING AND PRESCALER
- enter 1 for Baud Rate Prescaler
- enter 17 for time segment before sample point
- enter 6 time segment after sample point
- enter 1 for Data (Re)Synchronization Jump Width
- Click GENERATE PROJECT (WARNING files modified will be overwritten)
Nearly finished .. additional code to configure CAN_STDBY must be added manually:
Add the following GPIO pin definition to atmel_start_pins.h:
#define CAN_STDBY GPIO(GPIO_PORTC, 13)
Add the GPIO pin setup into system_init() in driver_init.c:
void system_init(void)
{
init_mcu();
gpio_set_pin_level(CAN_STDBY, false);
// Set pin direction to output
gpio_set_pin_direction(CAN_STDBY, GPIO_DIRECTION_OUT);
gpio_set_pin_function(CAN_STDBY, GPIO_PIN_FUNCTION_OFF);
Finally, invoke the CAN_0_example() from main() to generate the test messages:
int main(void)
{
atmel_start_init();
while (true) {
delay_ms(500);
gpio_toggle_pin_level(LED0);
CAN_0_example();
}
}
With this working it should be possible to see the CAN messages logged on the external tool - see previous guide for details about setting up PEAK PCAN-USB Adapter.
CAN peripheral timing register details
This section provides some detail on the configuration of the CAN bus timing registers ("normal" mode of CAN 2.0, not the FD/BR enhancements). For authoritative reference please consult suitable documentation such as Understanding Microchip’s CAN Module Bit Timing AN754
A typical development task would be to integrate some new device into a system where the CAN bus is already established at a certain bit rate, e.g. 250 kb/s, 500 kb/s. The actual bit rate used is determined by considering a number of criteria. The maximum reliable bit rate that can be achieved on a given bus topology is impacted by the length of the bus, so physical bus topology (bus length and number of nodes) is probably the most significant factor.
This guide will take the desired CAN bus bit rate to be 500 kb/s. In this very simple example, the CPU clock is already configured with 12 Mhz source from GCLK1 - note that 12 Mhz is a multiple of the desired CAN bus rate and it should be possible to also clock the CAN bus from GCLK1 without requiring any further clock division or prescale factor.
Refer to the diagram above (reproduced from Understanding Microchip’s CAN Module Bit Timing AN754). The 4 discrete time segments comprise one nominal bit time (tBIT):
- Synchronization segment
- Propogation segment
- Phase segment 1
- Phase segment 2
tBIT is a multiple of the clock source supplied to the CAN peripheral (tOSC). On the SAMe54, tOSC is supplied by a GCLK module (which in turn is derived from the 12 Mhz crystal oscillator XOSC1). The CAN module provides further means to adjust tOSC by way of the baud rate prescaler (BRP). In this example, tOSC of 12 Mhz is used directly with no prescaling (uses BRP of 1). Regardless, the output of the BRP is taken as the time quanta (tQ) - the segment timing values (as entered into the CAN module configuration in the previous section) are specified in terms of a number tQ.
The total number of time quanta comprising a bit time is a function of the oscillator frequency tOSC, baud rate prescale, and the desired CAN bit rate (500 kb/s). For this example, baud rate prescale is 1 (so it can be ignored), so taking 1/tOSC as tQ, and dividing this into the CAN bit-time tBIT results in the following simplified expression ...
tBIT / tOSC = (1/500k) / (1/12M) = 1/500k * 12M = 12M / 500k = 24
... resulting in one bit-time of 24 time quanta.
In order to determine the actual segment values to be used, the sample point (as a percentage of the nominal bit time) must be chosen. A general practice is to start with 75% sample point.
First, revisiting the programmable registers:
- NTSEG1: nominal time segment before sample point - sum of Prop_seg and Phase_Seg1
- NTSEG2: time segment after sample point
Starting with NTSEG2:
- NTSEG2 = 24 * 25% = 6
- NTSEG1 = 24 - 6 - 1 = 17
Notes:
- NTSEG1 is the sum of PhaseSeg1 and Prop segment time.
- NTSEG1 does not include SyncSeg time, so NTSEG1 is adjusted (-1) to account for the length of SyncSeg (fixed at 1 tQ)
Additional note about using START configurator: NTSEG values as determined above are NOT the actual values programmed to CAN configuration registers. As stated in the SAMD5x/E5x Data Sheet "actual interpretation by the hardware of this value is such that one more than the programmed value is used". Therefore, to program these registers, you would subtract 1 from the calculated segment values. START decrements the input values by 1 automatically. This can be seen in the file hpl_can_config.h.
SJW becomes important for properly calibrating the system accounting for component tolerance and bus length, but not critical for this lab experiment. 1 is used for re-syn jump width with no further justification.