Introduction to embARC OSP - foss-for-synopsys-dwc-arc-processors/embarc_osp GitHub Wiki

Overview

The embARC Open Software Platform (OSP) consists of software and documentation to accelerate the development of embedded systems based on DesignWare® ARC® processors.

  • Comprehensive suite of free and open-source software, including drivers, operating systems, middleware and utilities for embedded software development on DesignWare® ARC® processors for IoT applications
  • Includes port of FreeRTOS OS operating system
  • Open-source networking (TCP/IP, IPv4, IPv6, 6lowPAN) and security (TLS/DTLS) protocol stack support
  • Packaged with common IoT protocol implementations, including MQTT, CoAP and LWM2M
  • Supported by free open source GNU Toolchain and premium MetaWare tools
  • Dedicated website with downloads, documentations and user forums

embARC OSP Software

The embARC OSP includes drivers, operating systems, middleware, and utilities ported to the ARC EM and HS family of processors. It provides developers with the choice of leading real-time operating systems (RTOSes) including FreeRTOS and ARC MQX RTOS (contact Synopsys representative for more information).

FreeRTOS is a scalable, compact and reliable operating system that is extremely popular among embedded software developers. Accompanying middleware and utilities include the TCP/IP stack lwIP, file system fatfs as well as TLS/DTLS, MQTT, CoAP, libcoap and LWM2M IoT protocol implementations.

Tools

Free software development tools built on the open-source Eclipse IDE and GNU toolchain are available for use with the embARC OSP, giving developers a flexible software environment with an IDE, compiler, debugger and utilities that are familiar to embedded developers.

The embARC OSP software is also supported by the commercially-available Synopsys ARC MetaWare Development Toolkit, providing developers the option to use a highly optimized toolchain for maximum code density and performance.

ARC EM and HS Processors

Synopsys' DesignWare ARC processors are 32-bit CPUs that SoC designers can optimize for a wide range of uses, from deeply embedded to high-performance host applications in a variety of market segments.

The ARC EM processor family is based on the scalable ARCv2 Instruction Set Architecture (ISA) and is optimized for performance efficiency (DMIPS/mW and DMIPS/mm2). The EM processors are highly-configurable and extensible, enabling designers to implement each core with the optimum combination of performance, code density, area and power consumption for the specific task or application.

The ARC HS processor family is based on the scalable ARCv2 ISA and is optimized to deliver maximum performance efficiency (DMIPS/mW and DMIPS/mm2) making it ideally suited for embedded applications with high-speed data and signal processing requirements. All HS processors are available in single-, dual- and quad-core configurations.

Development Platforms

ARC EM Starter Kit

The embARC Open Software Platform has been ported to Synopsys' ARC EM Starter Kit, a low-cost, versatile software development board consisting of pre-installed FPGA images of ARC EM Processors with peripherals and a software package. The ARC EM Starter Kit enables rapid software development, code porting, software debugging, and profiling for the EM4, EM6, EM5D, EM7D, EM9D and EM11D processors.

ARC HS Development Kit

The ARC HS Development Kit (HSDK) Platform supports the ARC HS34, HS36 and HS38x4 quad core processors running at 1GHz. The ARC HSDK features 256 kByte of on-chip SRAM and 4 GByte of DDR3-SDRAM. The software available from Synopsys for the ARC HSDK includes pre-built SMP Linux image (plus the U-boot bootloader) and the embARC OSP distribution for embedded systems. embARC OSP source code includes bare metal and FreeRTOS device drivers and example applications. Code development is made easy using the MetaWare Development Toolkit, MetaWare Lite tools or the ARC GNU Tool Chain.

ARC IoT Development Kit

The ARC IoT Development Kit (IoTDK) Platform supports the DesignWare ARC Data Fusion IP Subsystem (DFSS). The DesignWare ARC DFSS is a complete, pre-verified, hardware and software solution optimized for a wide range of ultra-low power IoT applications. It is designed for fast and easy integration within a larger system context, including ARC EM9D, an extensive collection of I/O functions and fast math (trigonometric) accelerator.