4029 IC - eclubiitk/EClub-Handbook GitHub Wiki

One of the most common requirements in digital equipment is counting. And the most common counting requirement has to do with time. From a basic digital clock (which is incorporated into most digitally-controlled appliances) to interval timers and event counters, the need for counting circuits is very great.

The 4029 IC is a presettable up/down counter which counts in either binary or decimal mode depending on the voltage level applied at binary/decimal input whenever a signal is recieved at the CLOCK.

Functioning

The pin connections are shown below

The internal schematic diagram of the 4029 is quite complex. However, we can’t reach the internal circuitry in any case, so the functional diagram to the right is far more useful for our purposes. Most of the designations are straightforward and intuitive.

• UP/DN Pin tells the counter in which direction to count. If its HIGH, the IC counts in up direction otherwise it counts in down direction.
• BIN/DEC Pin causes the counter to operate in binary mode if it's HIGH, while a LOW input switches it to decimal (sometimes called decade) mode.
• CIN Pin activates or deactivates the counter. It won't count if the Pin is HIGH. When CIN goes to LOW, the counter operates normally.
• PE The PE input is the preset enable line. When this line is LOW, the counter operates normally. However, when PE becomes HIGH, the logic signals present on the four jam input lines get copied directly to the four bits of the counter, overriding any prior count.

Multiple 4029s

If multiple 4029s are cascaded for a larger count, each IC represents a higher order. All up/dn pins are connected together and driven from a common signal, as are all bin/dec lines. The COUT of a 4029 is connected to the CIN of next 4029.

If CIN is HIGH, the counter won’t count at all. When CIN goes to LOW, the counter operates normally. Then, when the counter reaches its terminal count (9 for decimal, 15 for binary on an up scale), or 0 (on down scale) depending on the states of up/dn and bin/dec), COUT goes to LOW. This is connected to the CIN line of the next IC to allow the next higher order of magnitude to count once. Then COUT goes to HIGH again.

This means when the lowest IC which counts, say, the units place goes to 9 the COUT of the IC sends a LOW signal to the CIN of the next 4029. The next 4029 is counting the tens place. Therefore it changes it's count from 0 to 1, if we had started counting from 0. Once again the CIN of the higher 4029 goes HIGH and the counter stops. This counter now waits for a LOW signal from the COUT of previous 4029.

The first counter IC in the set, representing the least significant digit, has its CIN line grounded to LOW so it will always count. The clock input, like up/dn and bin/dec, is fed to all 4029s in an extended counter circuit. This is the signal that represents whatever is to be counted. Any 4029 that is enabled by having its CIN line at logic 0 will change state to the next count when the clock rises from logic 0 to logic 1. Any changes to the CIN and COUT lines will occur just after that rising edge, and so will be ready for the next clock pulse.

The datasheet is available here