x32_sign - dspsandbox/Canvas GitHub Wiki

Description

Logic SIGN. Returns the sign bit (two's complement representation).

Ports

Name Direction Width Comment
in Rx 32 bit
out Tx 1 bit out=1 IF in<1
out=0 OTHERWISE

Pipeline latency (clk @ 125 MHz)

0 clk cycles.

VHDL

x32_sign.vhd

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