x32_delayVariable - dspsandbox/Canvas GitHub Wiki
images/DSP-modules/x32_delayVariable.png
Description
Variable DELAY based on a 256 elements ring buffer.
The delay module is active for clr=0. When clr=1, the input to the ring buffer and the output port are both set to 0. Note that 256 clk cycles with clr=1 are required to fully clear the ring buffer.
Ports
| Name | Direction | Width | Comment |
|---|---|---|---|
| in | Rx | 32 bit | |
| delay | Rx | 32 bit | Min: 2 Max: 256 |
| clr | Tx | 1 bit | |
| out | Tx | 32 bit | out=RING_BUFFER_OUT IF clr==0 out=0 IF clr==1 |
Pipeline latency (clk @ 125 MHz)
2-256 clk cycles.