x32_compareSmaller - dspsandbox/Canvas GitHub Wiki

Description

Logic COMPARE SMALLER gate.

Ports

Name Direction Width Comment
in0 Rx 32 bit
in1 Rx 32 bit
out Tx 1 bit out=1 IF in0<in1
out=0 OTHERWISE

Pipeline latency (clk @ 125 MHz)

1 clk cycle.

VHDL

x32_compareSmaller.vhd

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