x1_switch - dspsandbox/Canvas GitHub Wiki

images/DSP-modules/x1_switch.png

Description

Logic SWITCH.

Ports

Name Direction Width Comment
in0 Rx 1 bit
in1 Rx 1 bit
sel Rx 1 bit
out Tx 1 bit out=out0 IF sel==0 out=out1 IF sel==1

Pipeline latency (clk @ 125 MHz)

1 clk cycle.

VHDL

x1_switch.vhd