x1_not - dspsandbox/Canvas GitHub Wiki
Description
Logic NOT gate.
Ports
| Name | Direction | Width | Comment |
|---|---|---|---|
| in | Rx | 1 bit | |
| out | Tx | 1 bit | out= ! in |
Pipeline latency (clk @ 125 MHz)
1 clk cycle.
Logic NOT gate.
| Name | Direction | Width | Comment |
|---|---|---|---|
| in | Rx | 1 bit | |
| out | Tx | 1 bit | out= ! in |
1 clk cycle.