x1_delay1Clk - dspsandbox/Canvas GitHub Wiki
images/DSP-modules/x1_delay1Clk.png
Description
1 clk DELAY.
Ports
| Name | Direction | Width | Comment |
|---|---|---|---|
| in | Rx | 1 bit | |
| out | Tx | 1 bit |
Pipeline latency (clk @ 125 MHz)
1 clk cycle.
images/DSP-modules/x1_delay1Clk.png
1 clk DELAY.
| Name | Direction | Width | Comment |
|---|---|---|---|
| in | Rx | 1 bit | |
| out | Tx | 1 bit |
1 clk cycle.