x1_compareEqual - dspsandbox/Canvas GitHub Wiki
images/DSP-modules/x1_compareEqual.png
Description
Logic COMPARE EQUAL gate.
Ports
| Name | Direction | Width | Comment |
|---|---|---|---|
| in0 | Rx | 1 bit | |
| in1 | Rx | 1 bit | |
| out | Tx | 1 bit | out=1 IF in0==in1 out=0 OTHERWISE |
Pipeline latency (clk @ 125 MHz)
1 clk cycle.