x1_and - dspsandbox/Canvas GitHub Wiki
Description
AND gate.
Ports
| Name | Direction | Width | Comment |
|---|---|---|---|
| in0 | Rx | 1 bit | |
| in1 | Rx | 1 bit | |
| out | Tx | 1 bit | out= in0 && in1 |
Pipeline latency (clk @ 125 MHz)
1 clk cycle.
AND gate.
| Name | Direction | Width | Comment |
|---|---|---|---|
| in0 | Rx | 1 bit | |
| in1 | Rx | 1 bit | |
| out | Tx | 1 bit | out= in0 && in1 |
1 clk cycle.