My first DSP design - dspsandbox/Canvas GitHub Wiki

Let's get started with a simple DSP design, which blinks the 8 LEDs of your Redpitaya.

images/My-first-DSP-design/redpitaya.gif

This tutorial assumes that you have installed, registered and configured the DSPsandbox-Canvas environment (see First steps...).

Start the Python GUI

  • Open the terminal / command line tool (if you have installed Anaconda on Windows, please use the Anaconda Navigator).
  • Navigate to the directory Canvas/Python_GUI.
  • Run python main.py on the command line.

Create a new project

  • Choose the option New.

images/My-first-DSP-design/newProject.png

  • Select the location and name of the design. Canvas automatically generates a containing directory. Note that the project name should include .prj termination, i.e. projectName.prj. If this is not the case, the .prj termination will be added automatically.

images/My-first-DSP-design/projectName.png

Enter server and FPGA settings

The SERVER and FPGA tags are used to switch between both GUI functionalities. Please check Configure Python GUI for their settings. There, you also find instructions on how to define your default settings.

  • Under SERVER you can set the server (IP and Port) and workspace (Id and Key) configurations.

images/My-first-DSP-design/settingsServer.png

  • Similarly, under FPGA you can set the device IP, Port and SSH credentials, i.e. User (U) and Password (P).

images/My-first-DSP-design/settingsFPGA.png

  • Alternatively, load directly the default settings by using Settings-> Load default in the Navigation menu.

Verify connectivity and credentials

  • Under SERVER press the button Verify. If the provided settings are correct, the following message should appear:

images/My-first-DSP-design/verifyServer.png

  • Under FPGA press the button Verify. If the provided settings are correct, the following message should appear:

images/My-first-DSP-design/verifyFPGA.png

Open mainCircuit.asc

  • Open the project directory by clicking Project->Inspect Project Directory in the Navigation menu.
  • Open the directory Input.
  • Open mainCircuit.asc with LTspice. You will see a blank schematic:

images/My-first-DSP-design/emptyLTspice.png

Edit mainCircuit.asc

These are the most used LTspice shortcuts when drawing a Canvas DSP design:

Action Key
New component F2
Draw wire F3
Delete F5
Duplicate F6
Move F7
Drag F8
Exit selection Esc

The first element we need is a counter. This is achieved as follows:

  • Add new component (F2): select Canvas/x32/Arithmetic/x32_add and press OK.
  • Add new component (F2): select Canvas/x32/Constant/x32_const and press OK.
  • Add new component (F2): select Canvas/x1/Constant/x1_const and press OK.
  • Move (F7) and wire (F3) them together as shown bellow:

images/My-first-DSP-design/counterLTspice.png

  • (Optional). Have a look at the documentation of the instantiated DSP modules.
  • (Optional). Assign an instance name to the x32_const and x1_const blocks. In the figure bellow we show how we set the instance name of the 32 bit constant to increment. Select the instance name to be visible. IMPORTANT: Do ONLY change the InstName attribute.

images/My-first-DSP-design/setConstNameLTspice.png

  • (Optional). Move (F7) the instance name to a convenient location. You can change the fontsize, justification... by right clicking on the instance name.

images/My-first-DSP-design/setNamesLTspice.png

We now add the logic that returns the sign of the counter, a not gate and the LEDs:

  • Add new component (F2): select Canvas/x32/Logic/x32_sign and press OK.
  • Add new component (F2): select Canvas/x32/Logic/x1_not and press OK.
  • Add new component (F2): select Canvas/x32/Port/x1_led<i> where <i>=0-7 and press OK.
  • Move (F7) and wire (F3) them together as shown bellow:

images/My-first-DSP-design/fullSchematicLTspice.png

Server requests

  • Under SERVER verify that Request NET/VHDL and Request SYNTH/IMPL are checked.
  • Click RUN SELECTED.

Since this design is already saved in the Canvas database, the whole procedure should not exceed 5s. After successful completion the following Log message appears:

images/My-first-DSP-design/runServer.png

  • (Optional). Inspect the project directory by clicking Project->Inspect Project Directory in the Navigation menu. You will see that besides the Input directory you have:
    • NET_input: contains the .net file corresponding to your input design.
    • NET_parsed: contains the parsed .net file, a sorted version of the previous .net file with unique instance names. The renamed instances are listed in connectionTable.txt.
    • VHDL: contains the automatically generated VHDL DSP module.
    • Zynq_PS: contains the log files of synthesis and implementation as well as the generated bitstream.

images/My-first-DSP-design/projectOutput.png

FPGA requests

Under FPGA:

  • Set the x1 constants you instantiate in your design. In this case we leave the constant named clear equal to 0.

images/My-first-DSP-design/setX1Const.png

  • Set the x32 constants. In this case we set increment such that the 32 bit counter overflows after 1s. Since the internal clock operates at 125 MHz, we set increment to 2^32/125000000.

images/My-first-DSP-design/setX32Const.png

  • Verify that Auto load after PS boot is set to ON. This option is used to automatically load constants and bitstream at boot of the device (e.g. after a power failure).

images/My-first-DSP-design/autoLoad.png

  • Verify that Config. FPGA, Load bitstream and Load constants are checked.

  • Click RUN SELECTED.

After successful completion the following Log message appears:

images/My-first-DSP-design/runFPGA.png

Power down/reboot

If needed, you can use the Python GUI to reboot your Redpitaya. Under FPGA, click Reboot and please wait until the following Log message appears:

images/My-first-DSP-design/reboot.png