IOP 16 Output Latch - douggilliland/IOP16 GitHub Wiki

VHDL Code

Entity

n generic is number of bits

-- GPIO interfaces
gpio3 <= w_gpio3;
gpio3_IO : entity work.OutLatch
generic map (n => 8)
	port map (
		dataIn		=> w_periphOut,
		clock			=> i_clk,
		load			=> w_wrGpio3,
		clear			=> not w_resetClean_n,
		latchOut		=> w_gpio3
		);

Calling

LOOPOPT7A	IOW	Reg2,WR_GPIO3	// REG2 HAS VALUE TO WRITE

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