IOP 16 ANSI Display - douggilliland/IOP16 GitHub Wiki

Table of Contents

Multicomp FPGA VGA

Programming Interface

  • Two addresses, Control/status and data access

Status Register

  • Register Select = 0
  • Read/Write = Read
    • d0 = RDRF = Receive Data Register Full (1 = data is ready to read)
    • d1 = TDRE = Transmit Data Register Empty (1 = transmit is ready to send out data)
    • d2 = DCD = Data Carrier Detect (0 = carrier present - hardwired)
    • d3 = CTS = Clear to Send (0 = Clear to Send - ready to accept data - hardwired)
    • d7 = IRQ = Interrupt Request (1 = Interrupt present)

Control Register

  • Register Select = 0
  • Read/Write = Write
    • d1,d0 = Control (11 = Master Reset)
    • d6,d5 = TC = Transmitter Control (RTS = Transmitter Interrupt Enable/Disable)
    • d7 = Interrupt Enable (1=enable interrupts)

Data Register

  • Register Select = 1
    • Read = Read data from the data register (not implemented due to kbd removal)
    • Write = Write data to the data register

ANSI ESC Codes

Example Code

  • Initialize the VDU
    • Init VDU hardware
    • Clear the screen
    • Set text color to yellow
    • Pass value to functions in Reg1
    • Returns value from runction in Reg0
  • Destroys Reg0, Reg1
INITVDU	LRI	0X00	0X03	RESET TERMINAL COMMAND
	IOW	0X00	0X0A	WRITE VDU CMD REG
	LRI	0X00	0X20	TX CTRLS RTS
	IOW	0X00	0X0A	WRITE VDU CMD REG
CLRSCR	LRI	0X01	0X0C	ANSI CLEAR THE SCREEN CMD
	JSR	WRVDU		WRITE OUT CHAR IN R1
YELLOW	LRI	0X01	0X1B	ESC SEQ FOR YELLOW CHARS
	JSR	WRVDU		WRITE OUT CHAR IN R1
	LRI	0X01	0X5B	[
	JSR	WRVDU		WRITE OUT CHAR IN R1
	LRI	0X01	0X33	3
	JSR	WRVDU		WRITE OUT CHAR IN R1
	LRI	0X01	0X33	3
	JSR	WRVDU		WRITE OUT CHAR IN R1
	LRI	0X01	0X6D	m 
	JSR	WRVDU		WRITE OUT CHAR IN R1
	RTS
  • Write out char in Reg0 to VDU
  • Destroys Reg1
WRVDU	JSR	WTVDUTXRDY		WAIT VDU TX READY
	IOW	0X01	0X0B		WRITE OUT R1 TO SCREEN
	RTS			
WTVDUTXRDY	IOR	0X00	0X0A	READ VDU STATUS
	ARI	0X00	0X02		TX EMPTY FLAG
	BEZ	WTVDUTXRDY		WAIT UNTIL TX EMPTY
	RTS
  • Write CR-LF to VDU
  • Destroys Reg1
VDUCRLF	LRI	0X01	0X0D	CR
	JSR	WRVDU		
	LRI	0X01	0X0A	LF
	JSR	WRVDU		
	RTS

Acknowledgments

These files are from Neal Crook's port of the VHDL code to support VGA files (as snagged 2019-04-08) for Grant Searle's Multicomp Retro-Computer. Neal describes the enhancements here.

Grant's projects re-create late 1970's and early 1980's era vintage computers using inexpensive FPGA cards. The various parts that make up retro-computers are in each of the folders.

Our RetroComputing Wiki page is here.

Ownership

  • Some of these files such as FPGA designs and software libraries were created by others.
    • There may be newer versions of these libraries "out there".
    • Some libraries even have the same names but don't work the same.
  • Many of these files were created by me based on the work of others.

Warning

  • Use at your own risk.
    • If you brick your part or it melt to a puddle, it's on you not me.
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