Innovus - dinokev6/Cadence-Notes GitHub Wiki
This page provides an example introductory run of the Innovus Place & Route flow. It shows the commands to be run for an example netlist generated from the Genus tutorial, and briefly describes what each command does.
Startup
Create a directory (preferably next to your Genus folder), and navigate into it.
mkdir innovus
cd innovus
Create this script in the directory.
This script configures the Cadence base directory, license directory, and license file so that a copy of Genus can be checked out.
It then adds the path to the Innovus binaries to $PATH.
Navigate to your cadence home directory, where your cds.lib is located.
Create a file named .cdsinit (or edit the existing one) and add this to it.
load "opt/local/cadence/INNOVUS181/tools/innovus/gift/AoT/VEXface/virLaunchInnovusIC61x.il"
This tells the CIW to load virLaunchInnovusIC61x.il, which adds Innovus as an option under Layout XL.
Source the startup.innovus.181 file in a tcsh.
$ tcsh
% source /path/to/startup.innovus.181
Now relaunch Cadence Virtuoso, and open Virtuoso Layout XL.
Note: This option only appears on Virtuoso Layout XL or GXL. Layout L will not have it.
Timing Setup
In order for Innovus to do timing analysis, constraints need to be supplied, similar to Genus.
The SDC file containing the constraints used in Genus to generate the netlist should be translated from Genus SDC syntax to the generic syntax using the write_sdc command at the end of the Genus flow.
Next, create a tcl script named design.view and edit it.
Change the directory in the script to somewhere that is close to the timing libraries and QX techfile.
Mine is symlinked, so it is in my cadence directory. You can do this with ln -s.
cd /home/du.566/cadence/GPDK45/
Create a constraint from an SDC file. The file supplied should be from the write_sdc output of your Genus run.
create_constraint_mode -name ALUConstraint -sdc_files [list synthesis/innovus/genus_outputs/ALUREG8bit.sdc]
Create an RC corner from the QX tech file.
create_rc_corner -name rc_typical -qx_tech_file gsclib045_all_v4.4/gsclib045_tech/qrc/qx/gpdk045.tch
Note: If you use the wrong file, you may get an unknown error along with a message to contact cadence. If this happens, try another file.
Create a library set for each timing corner.
create_library_set -name Slowlib1v0 -timing {gsclib045_all_v4.4/gsclib045/timing/slow_vdd1v0_basicCells.lib}
create_library_set -name Fastlib1v0 -timing {gsclib045_all_v4.4/gsclib045/timing/fast_vdd1v0_basicCells.lib}
create_library_set -name Slowlib1v2 -timing {gsclib045_all_v4.4/gsclib045/timing/slow_vdd1v2_basicCells.lib}
create_library_set -name Fastlib1v2 -timing {gsclib045_all_v4.4/gsclib045/timing/fast_vdd1v2_basicCells.lib}
Create delay corners associating a library set and RC corner.
Note: There's no point in doing this with a single RC corner, but with multiple you can create more delay corners.
This is still required though, as analysis views take delay corners.
create_delay_corner -name DCSlow -library_set {Slowlib1v0} -rc_corner {rc_typical}
create_delay_corner -name DCFast -library_set {Fastlib1v0} -rc_corner {rc_typical}
create_delay_corner -name DCSlow1v2 -library_set {Slowlib1v2} -rc_corner {rc_typical}
create_delay_corner -name DCFast1v2 -library_set {Fastlib1v2} -rc_corner {rc_typical}
Create analysis views associating a constraint (SDC), and a delay corner. This is the final result of this view file, as it binds timing constraints with best case / worst case post route timing information, allowing Innovus to perform timing analysis and optimization.
For Hold analysis, use the fast corner. For Setup, use the slow corner.
create_analysis_view -name setup -constraint_mode ALUConstraint -delay_corner {DCSlow}
create_analysis_view -name hold-constraint_mode ALUConstraint -delay_corner {DCFast}
create_analysis_view -name setup1v2 -constraint_mode ALUConstraint -delay_corner {DCSlow1v2}
create_analysis_view -name hold1v2 -constraint_mode ALUConstraint -delay_corner {DCFast1v2}
Finally, attach the analysis view for setup and hold analysis.
set_analysis_view -setup {setup setup1v2] -hold {hold hold1v2}
The final design.view is shown below.
###cd to Technology Library Path###
cd /home/du.566/cadence/GPDK45/
###Create Constraint from SDC File###
create_constraint_mode -name ALUConstraint -sdc_files [list synthesis/innovus/genus_outputs/ALUREG8bit.sdc]
###Create RC Corner from QX Techfile###
create_rc_corner -name rc_typical -qx_tech_file gsclib045_all_v4.4/gsclib045_tech/qrc/qx/gpdk045.tch
###Create Library Set for Each Corner###
create_library_set -name Slowlib1v0 -timing {gsclib045_all_v4.4/gsclib045/timing/slow_vdd1v0_basicCells.lib}
create_library_set -name Fastlib1v0 -timing {gsclib045_all_v4.4/gsclib045/timing/fast_vdd1v0_basicCells.lib}
create_library_set -name Slowlib1v2 -timing {gsclib045_all_v4.4/gsclib045/timing/slow_vdd1v2_basicCells.lib}
create_library_set -name Fastlib1v2 -timing {gsclib045_all_v4.4/gsclib045/timing/fast_vdd1v2_basicCells.lib}
###Create Delay Corner for Each Library Set and RC Corner###
create_delay_corner -name DCSlow -library_set {Slowlib1v0} -rc_corner {rc_typical}
create_delay_corner -name DCFast -library_set {Fastlib1v0} -rc_corner {rc_typical}
create_delay_corner -name DCSlow1v2 -library_set {Slowlib1v2} -rc_corner {rc_typical}
create_delay_corner -name DCFast1v2 -library_set {Fastlib1v2} -rc_corner {rc_typical}
###Create Analysis View for Each Constraint and Delay Corner###
create_analysis_view -name setup -constraint_mode ALUConstraint -delay_corner {DCSlow}
create_analysis_view -name hold-constraint_mode ALUConstraint -delay_corner {DCFast}
create_analysis_view -name setup1v2 -constraint_mode ALUConstraint -delay_corner {DCSlow1v2}
create_analysis_view -name hold1v2 -constraint_mode ALUConstraint -delay_corner {DCFast1v2}
###Set Analysis Views for Setup and Hold
set_analysis_view -setup {setup setup1v2] -hold {hold hold1v2}
Main Run
The design will now be placed and routed through another script.
Create a script in the Innovus folder named design.tcl and edit it.
Set the process node. This will be used for optimization purposes by Innovus during later stages.
setDesignMode -process 45
Set the netlisttype to verilog and the path to the netlist output by Genus.
set init_design_netlisttype { Verilog }
set init_verilog { /home/du.566/cadence/GPDK45/synthesis/innovus/genus_outputs/ALUREG8bit.v }
Set the technology, cell abstract information and the MMMC view created earlier.
set init_oa_ref_lib { gsclib045 giolib045 gsclib045_tech }
set init_abstract_view { abstract }
set init_layout_view { layout }
set init_oa_default_rule { LEFDefaultRouteSpec }
set init_mmmc_file { /home/du.566/cadence/GPDK45/synthesis/innovus/ALU.view }
The oa_ref_libs are the standard cell libraries referenced inside the cds.lib in your Virtuoso directory.
The oa_default_rule chooses the DRC information within the tech LEF (.tlef) attached to the technology library.
The mmmc_file contains all timing information.
Set the power and ground net names for this design.
set init_pwr_net { VDD! }
set init_gnd_net { VSS! }
Tell Innovus to autogenerate vias rather than pick from the library, and initialize the design.
setGenerateViaMode -auto true
init_design
Specify the floorPlan dimensions of the design.
floorPlan -site CoreSite -r 1 0.9 1.0 1.0 1.0 1.0
The -site option is mandatory, and creates a core row site. The -r option allows you to specify the ratio, and the following numbers specify aspectRatio, rowDensity, marginLeft, marginBottom, marginRight marginTop.
Connect the global power nets to the standard cell power and ground pins in schematic.
globalNetConnect VDD! -pin VDD -type pgpin
globalNetConnect VSS! -pin VSS -type pgpin
If you don't know what the name of the standard cell power and ground pins are, open up the layout and find them. They may not be the same as in schematic. If you don't specify the correct pin names, Innovus will not find them, and will not connect your global power nets to your standard cells.
Route the power grid.
addStripe -nets { VDD! VSS! } -layer Metal11 -direction horizontal -width 1.8 -spacing 4 -set_to_set_distance 10
addStripe -nets { VDD! VSS! } -layer Metal10 -direction vertical -width 1.8 -spacing 4 -set_to_set_distance 10
sroute
addStripe adds the power grid with the specified horizontal and vertical metals.
-width defines how wide the metals are in μm.
-spacing defines the space between VDD and VSS stripes in μm.
-set_to_set_distance defines the space between each VDD stripe or VSS stripe in μm.
The metals selected for each direction should conform with HVH or VHV.
Place design with auto pin placement.
setPlaceMode -place_global_place_io_pins true
place_design
Configure CCOpt to do Clock Tree Synthesis.
set_ccopt_property use_inverters true
set_ccopt_property target_skew 116ps
set_ccopt_property target_max_trans 150ps
#setOptMode -usefulSkew false
ccopt_design
CCOpt (Clock Concurrent Optimization) does optimization concurrently with clock tree synthesis, and running this command will generate a clock tree as well as reduce total negative slack (TNS).
A part of this optimization is useful skew, where the optimizer performs time borrowing between sequential cells to optimize for slack. If later on you see extremely high skew in your clock tree, use setOptMode -usefulSkew false, and check that your design is constrained realistically, and that you do not have multiple nanoseconds of negative slack.
Add filler cells.
addFiller -cell FILL1 FILL2 FILL4 FILL8 FILL16 FILL32 FILL64 -prefix FILL -fitGap
addFiller -cell DECAP2 DECAP3 DECAP4 DECAP5 DECAP6 DECAP7 DECAP8 DECAP9 DECAP10 -prefix DECAP -fitGap
You should specify all available fill cells to this command so that it can select the appropriate ones to meet 100% core density.
Route the design.
routeDesign
Report timing for timing aware metal fill, and add the metal fill.
report_timing
addMetalFill -timingAware sta
If you want to connect the fill nets to power, supply the -nets { VDD! VSS! } option.
The final script is shown below.
setDesignMode -process 45
set init_design_netlisttype { Verilog }
set init_verilog { /home/du.566/cadence/GPDK45/synthesis/innovus/genus_outputs/ALUREG8bit.v }
set init_oa_ref_lib { gsclib045 giolib045 gsclib045_tech }
set init_abstract_view { abstract }
set init_layout_view { layout }
set init_oa_default_rule { LEFDefaultRouteSpec }
set init_mmmc_file { /home/du.566/cadence/GPDK45/synthesis/innovus/ALU.view }
set init_pwr_net { VDD! }
set init_gnd_net { VSS! }
setGenerateViaMode -auto true
init_design
floorPlan -site CoreSite -r 1 0.9 1.0 1.0 1.0 1.0
globalNetConnect VDD! -pin VDD -type pgpin
globalNetConnect VSS! -pin VSS -type pgpin
addStripe -nets { VDD! VSS! } -layer Metal11 -direction horizontal -width 1.8 -spacing 4 -set_to_set_distance 10
addStripe -nets { VDD! VSS! } -layer Metal10 -direction vertical -width 1.8 -spacing 4 -set_to_set_distance 10
sroute
setPlaceMode -place_global_place_io_pins true
place_design
set_ccopt_property use_inverters true
set_ccopt_property target_skew 116ps
set_ccopt_property target_max_trans 150ps
ccopt_design
addFiller -cell FILL1 FILL2 FILL4 FILL8 FILL16 FILL32 FILL64 -prefix FILL -fitGap
addFiller -cell DECAP2 DECAP3 DECAP4 DECAP5 DECAP6 DECAP7 DECAP8 DECAP9 DECAP10 -prefix DECAP -fitGap
routeDesign
report_timing
addMetalFill -timingAware sta
GUI
At this point, the design is fully routed. Open the GUI by typing win in the Innovus terminal when the script finishes. This will bring up the main Innovus window.
You can also view the clock tree by typing ctd_win in the Innovus terminal. This will bring up the clock tree debugger.
Timing
To report the timing, use the report_timing command.
By default, this will report the setup time of the single worst path.
innovus #> report_timing
###############################################################
# Generated by: Cadence Innovus 18.12-s106_1
# OS: Linux x86_64(Host ID ece-d01181524s.coeit.osu.edu)
# Generated on: Thu Feb 27 09:34:14 2020
# Design: ALUREG8bit
# Command: report_timing > timing.log
###############################################################
Path 1: MET Setup Check with Pin OREGZ_Q_reg[0]/CK
Endpoint: OREGZ_Q_reg[0]/D (^) checked with leading edge of 'clk1'
Beginpoint: IREG1_Q_reg[1]/Q (^) triggered by leading edge of 'clk1'
Path Groups: {clk1}
Analysis View: setup
Other End Arrival Time 0.011
- Setup 0.102
+ Phase Shift 3.500
= Required Time 3.409
- Arrival Time 3.384
= Slack Time 0.025
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.010
= Beginpoint Arrival Time 0.010
+----------------------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival | Required |
| | | | | Time | Time |
|---------------------------+--------------+----------+-------+---------+----------|
| IREG1_Q_reg[1] | CK ^ | | | 0.010 | 0.035 |
| IREG1_Q_reg[1] | CK ^ -> Q ^ | DFFQX2 | 0.277 | 0.287 | 0.312 |
| ALU/mul_35_23_g1541__8780 | B ^ -> Y ^ | AND2X1 | 0.178 | 0.465 | 0.490 |
| ALU/mul_35_23_g1454__3772 | A ^ -> S v | ADDFX1 | 0.313 | 0.778 | 0.803 |
| ALU/mul_35_23_g1441__7114 | CI v -> S ^ | ADDFHXL | 0.259 | 1.037 | 1.062 |
| ALU/mul_35_23_g1427__1474 | CI ^ -> CO ^ | ADDFX1 | 0.189 | 1.226 | 1.251 |
| ALU/mul_35_23_g1423__9906 | CI ^ -> CO ^ | ADDFX1 | 0.192 | 1.417 | 1.442 |
| ALU/mul_35_23_g1420__1840 | CI ^ -> CO ^ | ADDFX1 | 0.194 | 1.611 | 1.636 |
| ALU/mul_35_23_g1419__7344 | CI ^ -> CO ^ | ADDFX1 | 0.202 | 1.814 | 1.838 |
| ALU/FE_RC_17_0 | B ^ -> Y v | NAND2BX1 | 0.077 | 1.890 | 1.915 |
| ALU/FE_RC_16_0 | B v -> Y ^ | NAND2X1 | 0.055 | 1.946 | 1.970 |
| ALU/mul_35_23_g1417__2703 | CI ^ -> CO ^ | ADDFX1 | 0.197 | 2.142 | 2.167 |
| ALU/FE_RC_41_0 | B ^ -> Y v | NAND2BX2 | 0.071 | 2.214 | 2.238 |
| ALU/FE_RC_40_0 | B v -> Y ^ | NAND2X2 | 0.056 | 2.269 | 2.294 |
| ALU/FE_RC_32_0 | B ^ -> Y v | NAND2BX2 | 0.063 | 2.332 | 2.357 |
| ALU/FE_RC_31_0 | B v -> Y ^ | NAND2X1 | 0.051 | 2.384 | 2.409 |
| ALU/mul_35_23_g1414__5266 | CI ^ -> S v | ADDFX1 | 0.283 | 2.666 | 2.691 |
| ALU/g6292__7675 | C v -> Y v | OR4XL | 0.247 | 2.914 | 2.939 |
| ALU/FE_RC_5_0 | A v -> Y ^ | INVX1 | 0.047 | 2.961 | 2.986 |
| ALU/FE_RC_4_0 | B ^ -> Y v | NAND2X2 | 0.061 | 3.022 | 3.047 |
| ALU/FE_RC_3_0 | B v -> Y ^ | NOR3X2 | 0.125 | 3.147 | 3.172 |
| ALU/g6254__4296 | B1 ^ -> Y v | AOI221X2 | 0.147 | 3.294 | 3.319 |
| ALU/FE_RC_0_0 | B v -> Y ^ | NAND2X2 | 0.090 | 3.384 | 3.409 |
| OREGZ_Q_reg[0] | D ^ | DFFHQX2 | 0.000 | 3.384 | 3.409 |
+----------------------------------------------------------------------------------+
To do Hold analysis, use setAnalysisMode. This will report the single worst case hold time as well.
innovus #> setAnalysisMode -checkType Hold
innovus #> report_timing
###############################################################
# Generated by: Cadence Innovus 18.12-s106_1
# OS: Linux x86_64(Host ID ece-d01181524s.coeit.osu.edu)
# Generated on: Thu Feb 27 09:37:33 2020
# Design: ALUREG8bit
# Command: report_timing > hold.log
###############################################################
Path 1: MET Early External Delay Assertion
Endpoint: Result[4] (^) checked with leading edge of 'clk1'
Beginpoint: OREG_Q_reg[4]/Q (^) triggered by leading edge of 'clk1'
Path Groups: {clk1}
Analysis View: hold1v2
Other End Arrival Time 0.000
- External Delay 0.010
+ Phase Shift 0.000
= Required Time -0.010
Arrival Time 0.056
Slack Time 0.066
Clock Rise Edge 0.000
+ Clock Network Latency (Prop) 0.003
= Beginpoint Arrival Time 0.003
+-------------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival | Required |
| | | | | Time | Time |
|---------------+-------------+--------+-------+---------+----------|
| OREG_Q_reg[4] | CK ^ | | | 0.003 | -0.063 |
| OREG_Q_reg[4] | CK ^ -> Q ^ | DFFQX2 | 0.053 | 0.055 | -0.010 |
| | Result[4] ^ | | 0.000 | 0.056 | -0.010 |
+-------------------------------------------------------------------+
Design Checks
Innovus can check for connectivity, drc, metal density, and process antenna. If you pass all of these, LVS and DRC should be (almost) clean.
verifyConnectivity -noAntenna -report design_conn.rpt
verify_drc -report design_drc.rpt
verifyMetalDensity -report design_density.rpt
verifyProcessAntenna -report design_antenna.rpt
These will generate reports that you can view. If you see errors with connectivity or drc, use the zoomTo x y -r radius command to zoom to coordinates and pinpoint the exact cause of the issue.
Saving
After you have passed all checks as well as timing, you can save the design to Virtuoso. Open the GUI, and go to File -> Save, or press F2. From here, you can select which library and cellview to save it as.
To save the SDF file, use write_sdf with the selected view.
write_sdf ALU.sdf
You can now export this to Incisive again to do postlayout simulations.