This page provides an introductory rundown on the NCLaunch portion of the Incisive Enterprise Simulator (IES).

Startup
Compiling Verilog

• Source Files
• Standard Cells

Elaboration

• Back Annotations

Simulation

Create a directory for Incisive in which you will run the simulator, and navigate into it.

$ mkdir incisive
$ cd incisive

Create a startup script.

$ vi startup.incisive.152

Paste the contents of this script into the file, and source it in a tcsh.

$ tcsh
% source incisive.startup.152

This script configures the Cadence base directory, license directory, and license file so that a copy of Incisive can be checked out. It then appends to the $PATH variable the path to the Incisive binaries.

Note: This script launches Incisive in 64bit mode.

Once the path is updated, you can run IES through the nclaunch command.

% nclaunch&

Once IES starts, you should see an option to select the run mode. Select Multiple-Step.

Single step bundles the ncvlog compiler, ncelab elaborator, and ncsim simvision simulator into a single command named IRUN. I've experienced some weird caching issues with IRUN, so this guide will be using the multi-step tool.

In IES, you should see on the left the file browser, and a virtual library managed by a cds.lib on the right.

On the top, there will be a tools menu that the various binaries can be invoked with.

Verilog source files can be compiled by using the Verilog Compiler... option in the tool menu.

Navigate in the file browser to the source files you want to compile.
Select them either individually or using ctrl click, then invoke the Tools -> Verilog Compiler...

Source files will be compiled into the virtual library, under the folder specified as the "work library". You can change which work library you would like to compile into through the dropdown menu.
Note: The dropdown menu will always default to what is specified as the default work library every time the Verilog Compiler... is invoked. The default work library can be configured by right clicking on a library and selecting set as work library .

Your files now show up on the right, in the specified work library (default worklib).

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If you are doing behavioral simulation, skip to Elaboration

Create a new library for compiling standard cells to through Edit -> Add -> New Library....

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This is to contain all the cells within a separate library that you won't have to look at. This allows you to find the modules you care about faster, as only IES cares about the cells, and displaying 400 objects in the GUI is extremely laggy.

Compile the fast_vdd1v0_basicCells.v file to the newly created library.
You can find this file under the verilog folder inside of the standard cell library that you used for Genus. Use the same file that you used as the library, just with a .v instead of a .lib extension.
Expand the library to verify that the cells are properly compiled.

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Expand the work library that your source files were compiled to, and expand the hierarchy of the stimulus file.

Select the top level module, and invoke Tools -> Elaborator....
In the options menu, enable Other Options; specify -timescale 1ns/1ns -sdf_verbose.

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The timescale option sets the default timescale for the simulator to use if a module doesn't have a timescale specified. This prevents the timescale undefined error, which occurs because IES requires all modules to have timescales defined.

The -sdf_verbose option forces the SDF annotator to log all annotated delays to the log file.

You should have created an SDF file at the end of your Genus run. Inside of your stimulus block you can use the $sdf_annotate system directive to perform automatic back annotations during elaboration.

$sdf_annotate ( “sdf_file” {, module_instance} {, “config_file”}
{, “log_file”} {, “mtm_spec”}
{, “scale_factors”} {, “scale_type”} );

The arguments are as follows.

"sdf_file"
    Specifies the path to the SDF file. Relative file paths, i.e 
    "~/genus/alu.sdf" can be used.
    The path must be in quotes.
    The SDF file can be in four different formats:
        Source - alu.sdf
        Compiled - alu.sdf.X
        Zipped - alu.sdf.gz
        Zipped & Compiled - alu.sdf.gz.X
    The file that Genus outputs is SDF source, using this is fine,  as the
    ncsdfc will automatically compile the sdf file.
module_instance
    Optional: Specifies the scope that the annotation takes place. If not 
    specified, the module containing the $sdf_annotate call will be set as
    module_instance.
    If this is not specified properly for a given SDF file, the elaborator will
    log a very low percentage annotated.
"config_file"
    Optional: Specifies a path to a configuration file to control the timing. 
    If you don't specify a config file, the annotator uses default settings.
    The path must be in quotes.
    For now, omit this.
"log_file"
    Optional: Specifies a path to a log file. If you use this, you must supply 
    -sdf_verbose as an argument to the elaborator.
    The path must be in quotes. If it is just a name, such as "sdf.log", it 
    will be placed in the IES launch directory.
"mtm_spec" 
    Optional: Specifies the delay values to annotate, in quotes, chosen from:
        "MINIMUM" - annotates minimum delay value.
        "TYPICAL" - annotates typical delay value.
        "MAXIMUM" - annotates maximum delay value.
        "TOOL_CONTROL" (default) - annotates from the command line option
        specified.
        If no command line options are specified, this defaults to TYPICAL.
    If using GPDK045's timing files, you should specify "MAXIMUM", as
    "TYPICAL" / "MINIMUM" causes the annotator to annotate blank values
    since those timing values are blank, resulting in ideal timing.
"scale_factors"
    Optional: Three positive real numbers that the SDF annotator uses to scale
    the minimum, typical, and maximum delay values.
    The syntax is "min_mult:typ_mult:max_mult"; the default is "1.0:1.0:1.0".
    Specifying this will override the config file.
"scale_type"
    Specifies how the annotator scales the timing specification, in quotes,
    chosen from:
        "FROM_MINIMUM" - scales from minimum timing specification.
        "FROM_TYPICAL" - scales from typical timing specification.
        "FROM_MAXIMUM" - scales from the maximum timing specification.
        "FROM_MTM" (default) - scales from the minimum, typical, and
        maximum timing specifications.
    You can leave this as default.

After elaborating, you should see an item under the snapshot library.

Expand this, select it, and invoke Tools -> Simulator.... You can leave the options default.

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The simvision window should now pop up, and you can press F2 to simulate.

If you encounter a warning (*W) or error (*F) during any of the steps, you can run nchelp <step> <errCode> in the shell that IES was launched from to get a description of the error.
For example, if you encounter the *F,CUMSTS error during elaboration, you can get more info.

% nchelp ncelab cumsts
nchelp: 15.20-s068: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
ncelab/cumsts =
	If any module has been compiled with a timescale directive,
	the elaborator requires that all modules be compiled with
	a timescale directive. Use the -messages flag to have the
	timescales for each module printed. Use -TIMESCALE option to
	provide a timescale directive for all modules that don't have one.