This page provides an introductory run down of the Genus synthesis flow. It shows the commands to be run for an example file, and briefly describes what each command does.
This guide configures Genus to be run in Physical Layout Estimation mode, and configures the libraries and search paths for the GPDK045 process.

Startup
Setup

• Configuring Libraries
• Configuring HDL Path

Read HDL
Elaboration
Design Constraints
Synthesis
Reports
Exporting to Place & Route

Create a directory for Genus in which you will run the program, and navigate into it.

$ mkdir genus
$ cd genus

Create a startup script.

$ vi startup.genus.181

Paste the contents of this script into the file, and source it in a tcsh.

$ tcsh
% source startup.genus.181

This script configures the Cadence base directory, license directory, and license file so that a copy of Genus can be checked out.
It then appends to the $PATH variable the path to the Genus binaries.

Note: This script should launch Genus in 64bit mode.

Once the path is updated, you can run Genus simply through the genus command.

% genus
TMPDIR is being set to /tmp/genus_temp_18772...
Cadence Genus(TM) Synthesis Solution.
Copyright 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Cadence and the Cadence logo are registered trademarks and Genus is a trademark
of Cadence Design Systems, Inc. in the United States and other countries.

Version: 18.12-s018_1, built Thu Oct 25 18:11:18 EDT 2018
Options: 
Date:    Fri Aug 16 16:59:24 2019
Host:    examplehost
OS:      Red Hat Enterprise Linux Workstation release 6.10 (Santiago)

Checking out license: Genus_Synthesis

Loading tool scripts...

Finished loading tool scripts (11 seconds elapsed).

WARNING: This version of the tool is 294 days old.
@genus:root: #>

The @genus:root: #> indicates that you are now in the genus shell, and you can now begin executing genus commands.

Create setup and run tcl scripts by running

@genus:root: #> write_template -split -outfile run.tcl

This will generate a setup script that can be configured to load the libraries, as well as a run script that can be configured to automate the synthesis run. -split separates the setup and run into two scripts, setup_run.tcl and run.tcl.

Edit the setup script and configure the library search paths. Additional environment variables are defined to simplify the paths. They can also be absolute filepaths.

set libpath /opt/local/cadence/design_kits/gpdk045/lan/flow/t1u1/reference_libs/GPDK045
set timingpath $libpath/gsclib045_all_v4.4/gsclib045/timing
set lefpath $libpath/gsclib045_all_v4.4/gsclib045/lef
set qrcpath $libpath/gsclib045_all_v4.4/gsclib045/qrc/qx
#######################################################################################
set_db / .init_lib_search_path [list $timingpath $lefpath $qrcpath]

For an example script, see this file.
This script is written to configure the libraries, but not the HDL search paths as they aren't necessary in this tutorial. This script covers everything in the Setup section of this guide.

The set_db / .init_lib_search_path tells Genus where to search for library files. When setting the technology files, LEF files, and QRC tech files, Genus will either search an absolute filepath, or within one of the directories specified with this command. The / indicates that the attribute will be set for the root level, configuring it for the entire Genus run. If / is used, a . must precede the attribute.

Note: If you want to specify multiple strings to an attribute in Genus, you must do so simultaneously using TCL List format. If you specify them sequentially, the new value will replace the old one.
Exceptions to this exist such as read_lefs -lef <leffile1> and read_lefs -add_lef <leffile2>; those accomplish the same thing as set_db.

Note: TCL list format can be specified using {a b} or [list a b $c]. Braces indicate that everything within should be interpreted as a string literal, therefore variable substitutions don't work, so we use the alternative.

Once the library search paths are specified, the libraries can be loaded.

set_db library fast_vdd1v0_basicCells.lib
set_db lef_library {gsclib045_tech.lef gsclib045_macro.lef gsclib045_multibitsDFF.lef}
set_db qrc_tech_file 

Specify all LEF files when using set_db lef_library. It is a good idea to specify the tech.lef first; if you fail to do so and specify the macro.lef first, Genus will warn you.

Note: By specifying the LEF files, Genus will automatically configure the interconnect_mode attribute from the default wireload value to ple. This sets the synthesis mode to Physical Layout Estimation (PLE), in which physical information is used by Genus to provide better closure with back-end tools.

Note: Again, if multiple LEF files are being specified using the set_db lef_library command, they must be specified simultaneously, otherwise the new library will replace the old one.

Similar to the init_lib_search_path attribute, specifying the library paths, the init_hdl_search_path tells Genus where to look when reading HDL files. The paths can be specified in the exact same way as the library paths, with multiple being concatenated in TCL list format.

set some_path1 /path/to/files1
set some_path2 /path/to/files2
set some_path3 $some_path1/morefiles

set_db / .init_hdl_search_path [list $some_path1 $some_path2 $some_path3]

If init_hdl_search_path is not set, it will default to searching in the current directory.
Alternatively, absolute filepaths can be used when reading HDL source files.

HDL files can be read into Genus using the read_hdl command. The files will be searched in order of the directories listed in the init_hdl_search_path attribute.
Absolute filepaths can be used as well.

@genus:root: #> genus read_hdl {top.v block1.v block2.v}

Unlike reading in attributes, HDL files can be read in sequentially.

@genus:root: #> read_hdl top.v
@genus:root: #> read_hdl block1.v
@genus:root: #> read_hdl block2.v

By default, Genus synthesizes Verilog files, and assumes they are written in Verilog-2001.

After reading in HDL files, the elaborate command can be used to elaborate the top-level design and its references.

@genus:root: #> elaborate

During elaboration, Genus will:

• Build data structures
• Infer registers
• Perform high-level HDL optimization such as dead code removal
• Check semantics

In order to perform elaboration, the technology libraries must be read in. If you fail to specify the tech libs, Genus will give you an error.
If there are unresolved modules, Genus will search for them in the paths specified in the init_hdl_search_path attribute.
If it cannot find some modules, it will report which when the elaboration completes.

Synopsis Design Constraints (SDC) can be used to supply parameters to Genus, such as timing information, drive, and loads. If these constrains are not applied, Genus will be unable to perform timing analysis or optimization during the syn_opt stage.
Genus uses a subset of Synopsis' language, and has additional commands for constraining a design. It also uses a different unit of time.
Upon export into another tool, such as PnR in Innovus, the write_sdc command can be used to automatically translate Genus constraints into a common SDC form with proper units.
By default, Genus uses picoseconds and femtofarads as units. This can be changed by using the set_time_unit and set_load_unit commands.

set_time_unit -nanoseconds 1.0
set_load_unit -femtofarads 1.0

The create_clock command supplies Genus with clock waveforms.
The most simple clock is provided in this script, a single clock named clk1, with a period of 1.0 nanoseconds (1 GHz), and distributed to all clock ports in the design.
By default, the duty cycle of this clock is 50%.

create_clock -name clk1 -period 1.0 [clock_ports]

The set_input_delay and set_output_delay commands set the delay on the signal at the input and output ports relative to a clock.
The input delay is added to the total path delay, and the output delay is subtracted from the required arrival time.

set_input_delay 0.1 -clock [get_clocks {clk1}] [all_inputs]
set_output_delay 0.1 -clock [get_clocks {clk1}] [all_outputs]

The set_driving_cell command specifies the driving cell on an input. The driving cell must be a part of the standard cell library.
If trying to drive a clock cell, the command must be set to [clock_ports], as [all_inputs] will not include clock pins.

set_driving_cell -cell INVX4 [all_inputs]
set_driving_cell -cell INVX1 [all_outputs]

The set_load command specifies the load capacitance on the output ports.

set_load 100.0 [all_outputs]

The entire script is shown below.

set_time_unit -nanoseconds 1.0
set_load_unit -femtofarads 1.0
create_clock -name clk1 -period 1.0 [clock_ports]
set_input_delay 0.1 -clock [get_clocks {clk1}] [all_inputs]
set_output_delay 0.1 -clock [get_clocks {clk1}] [all_outputs]
set_driving_cell -cell INVX4 [all_inputs]
set_driving_cell -cell INVX1 [all_outputs]
set_load 100.0 [all_outputs]

The script can then be read into Genus using the read_sdc command.

@genus:root: #> read_sdc ALU.sdc

Genus will report if any commands failed.

Genus performs synthesis in three steps:

1. Synthesize to generic logic
2. Map to the technology library and perform incremental optimization (IOPT) to improve timing, area, and fix DRC violations.
3. Optimize the netlist to meet timing constraints, or balance total negative slack (TNS) according to cost groups.

@genus:root: #> syn_generic
@genus:root: #> syn_map
@genus:root: #> syn_opt

In order to generate a report, you must be within the design/ directory of the Genus Design Hierarchy. The vcd and vls commands can be used to navigate within the Hierarchy.

@genus:root: #> vcd designs
@genus:root:.designs #> vls
./              alu/
@genus:root:.designs #> vcd alu

The report_timing command can be used to generate a timing report.

@genus:design:alu: #> report_timing

The report_gates command can be used to generate a report listing all the gates, instances, and total area of instances.

@genus:design:alu #> report_gates
============================================================
  Generated by:           Genus(TM) Synthesis Solution 18.12-s018_1
  Generated on:           Aug 19 2019  02:34:04 am
  Module:                 alu
  Operating conditions:   PVT_1P1V_0C 
  Interconnect mode:      global
  Area mode:              physical library
============================================================

                              
   Gate    Instances   Area       Library    
---------------------------------------------
ADDFX1            35  179.550    fast_vdd1v0 
ADDHX1             6   22.572    fast_vdd1v0 
AND2X1            43   58.824    fast_vdd1v0 
AO22X1             3    8.208    fast_vdd1v0 
AOI211X1           3    7.182    fast_vdd1v0 
AOI21XL            2    3.420    fast_vdd1v0 
AOI221X1          15   35.910    fast_vdd1v0 
AOI22XL            9   18.468    fast_vdd1v0 
AOI2BB1XL          4    8.208    fast_vdd1v0 
AOI31X1            2    4.104    fast_vdd1v0 
AOI32X1            3    7.182    fast_vdd1v0 
CLKXOR2X1          1    2.736    fast_vdd1v0 
INVX1             31   21.204    fast_vdd1v0 
INVX2              3    3.078    fast_vdd1v0 
MX2X1             11   26.334    fast_vdd1v0 
MXI2XL             4    9.576    fast_vdd1v0 
NAND2BXL           4    5.472    fast_vdd1v0 
NAND2XL           24   24.624    fast_vdd1v0 
NAND3BX1           1    2.052    fast_vdd1v0 
NAND3BXL           2    3.420    fast_vdd1v0 
NAND4BBXL          1    3.078    fast_vdd1v0 
NAND4XL            1    1.710    fast_vdd1v0 
NOR2BX1            7    9.576    fast_vdd1v0 
NOR2XL            23   23.598    fast_vdd1v0 
OA22X1             5   11.970    fast_vdd1v0 
OAI211X1          12   20.520    fast_vdd1v0 
OAI21XL            4    6.840    fast_vdd1v0 
OAI221X1           9   21.546    fast_vdd1v0 
OAI222XL           2    5.472    fast_vdd1v0 
OAI22XL            4    8.208    fast_vdd1v0 
OAI2BB1X1         14   23.940    fast_vdd1v0 
OAI31X1            1    2.052    fast_vdd1v0 
OAI32X1            2    4.788    fast_vdd1v0 
OR2X1             14   19.152    fast_vdd1v0 
OR4X1              1    2.052    fast_vdd1v0 
XNOR2X1           22   52.668    fast_vdd1v0 
---------------------------------------------
total            328  669.294                


                                        
     Type      Instances   Area  Area % 
----------------------------------------
inverter              34  24.282    3.6 
logic                294 645.012   96.4 
physical_cells         0   0.000    0.0 
----------------------------------------
total                328 669.294  100.0 

The report_area command can be used to show the area of each block.

@genus:design:alu #> report_area
============================================================
  Generated by:           Genus(TM) Synthesis Solution 18.12-s018_1
  Generated on:           Aug 19 2019  02:39:40 am
  Module:                 alu
  Operating conditions:   PVT_1P1V_0C 
  Interconnect mode:      global
  Area mode:              physical library
============================================================

Instance Module  Cell Count  Cell Area  Net Area   Total Area 
--------------------------------------------------------------
alu                     328    669.294   468.172     1137.466 

The gate level netlist can be exported using the write_hdl command, redirecting output to a file with >. If the redirection is not used, the netlist will be printed to stdout.

@genus:design:alu #> write_hdl > ../innovus/aluNetlist.v

The write_sdc command translates the original Genus specific syntax to a more verbose common form that is compatible with Innovus.

@genus:root: #> write_sdc > ../innovus/alu.sdc

The Standard Delay Format (SDF) file containing delays of the synthesized netlist can be exported using the write_sdf command, again redirecting output to a file with >.

@genus:design:alu #> write_sdf > alu.sdf

Show all settings

vls -long -attribute /