Xeng_tvg - david-macmahon/wiki_convert_test GitHub Wiki

Block: X-Engine TVG (xeng_tvg) Block Author: Jason Manley Document Author: Jason Manley

Summary

Basic test vector generator for CASPER X-engines.

Mask Parameters

Parameter Variable Description
Number of Antennas ((2^n)) ant_bits Bitwidth of the number of antennas in the system.
Bitwidth of Samples in bits_in Bitwidth of component of the input.
X integration length ((2^n)) x_int_bits Bitwidth of X-engine accumulation length.
Sync Pulse Period ((2^n)) sync_period Bitwidth of number of valids between sync pulses.

Ports

Port Dir Data Type Description
tvg_sel in ufix_2_0 TVG selection. 0=off (passthrough), 1-3=TVG select.
data_in in inherited: bits_in*4 Data in for passthrough.
valid_in in boolean Valid in made available for passthrough.
sync_in in boolean Sync in made available for passthrough.
data_out out inherited: bits_in*4 ???
sync_out out boolean ???
valid_out out boolean ???

Description

This block generates data in a format suitable for input to a CASPER X-engine. The tvg_sel line selects the TVG. If set to zero, it is configured for passthrough and all input signals are propagated to the output (TVG is off). Values one through three select a TVG pattern. In this case, sync pulses are generated internally and valid data is output all the time. The three patterns are as follows:

  1. Inserts a counter representing the antenna number. All real values count up from zero and imaginary values counting down from zero. ie., antenna four would have the value (4 - 4i) inserted.
  2. Inserts the same constant for all antennas: (\textrm{Pol}{1 real}=0.125), (\textrm{Pol}{1 imag}=-0.75), (\textrm{Pol}{2 real}=0.5) and (\textrm{Pol}{2 imag}=-0.25)
  3. User selectable values for each antenna. Input registers named tv0 through tv7 are input cyclically. Each value is input for x_int_bits clocks.

Category:Block Documentation