Vegas_FPGA_Register_Definitions - david-macmahon/wiki_convert_test GitHub Wiki

Synchronization and arming

The sync generator provides a periodic sync signal and a master reset signal. The master reset signal is intended to indicate the PPS pulse that represents time zero.

The sync generator contains two registers:

  • sg_period - 32 bit sync period in FPGA cycles. The actual sync period will be 2 cycles longer than the value set to this register.
  • sg_sync - A multi-bit register with the following functions:
    • bit 4 - sync period select. This should always be 1.
    • bit 3 - not used
    • bit 2 - PPS enable. This bit is ANDed with the incoming PPS pulse. If it is zero, the PPS pulse will have no affect on the master reset.
    • bit 1 - Sync disable. This bit is inverted and ANDed with the sync pulse output. Thus if it is set to one no sync pulses will be generated.
    • bit 0 - Software PPS. A rising edge on this bit is ORed with the (PPS & PPS_enable) signal. Thus to have complete software control of when the PPS signal is generated, set PPS enable to zero and toggle Software PPS from zero to one when a PPS is desired.

In addition, bit 0 of the arm register should be set to one then zero to indicate that the following PPS will be used as the master reset.

The typical initialization sequence when an external PPS signal is present is as follows:

  1. Set sg_period appropriately
  2. Set sg_sync to 0x12 This disables output sync pulses and PPS
  3. Set arm to 0x00
  4. Set arm to 0x01
  5. Set arm to 0x00
  6. Set sg_sync to 0x14 This allows the PPS to come through and the sync pulses

If no external PPS is present, the last step would be

  • Set sg_sync to 0x11 This provides a positive edge on the Software PPS generating a fake PPS.
Note

Currently (2012.03.09) there is a bug where the switching signal generator uses the master reset signal as its reset, which is incorrect because the master reset will pulse with every PPS. Instead, it should use the spead_rst signal. A temporary work around is to ensure that bit 2 (PPS enable) of sg_sync is set to 0.

Switching Signal Generator (SSG)

The switching signal generator specifications and schematics are detailed in this file 1.

For reference they are copied here:

Inputs on GPIO-B:

  • bit 3 - Blank
  • bit 2 - Cal
  • bit 1 - Sig/Ref
  • bit 0 - Advanced Sig/Ref

Outputs on GPIO-A:

  • bit 5 - Internal - This simply connects to an LED on the distribution box for status indication. Has no other function
  • bit 4 - External - This simply connects to an LED on the distribution box for status indication. Has no other function
  • bit 3 - Blank
  • bit 2 - Cal
  • bit 1 - Sig/Ref
  • bit 0 - Advanced Sig/Ref

Each state of the SSG switching sequence is represented by a value in the ssg_bram.

The SSG is clocked by the "spectrum tick" which in Mode 1 is hard coded to 256 FPGA clock cycles.

The spectrum tick clocks two count-limited counters, the cycle_limit and the dur_len.

The maximum value of the cycle_limit counter is set by the length register. When cycle_limit == length, the ssg_bram address counter is reset. Thus the length register sets the overall length of the switching signal pattern in units of spectrum ticks.

The maximum value of the dur_len counter is set by the top 27 (out of 32) bits output by the ssg_bram. When the dur_len counter reaches this value, the ssg_bram address counter is incremented. Thus, the top 27 bits of a given switching state indicate the number of spectrum ticks to remain in that state.

The ssg_bram address counter is also reset when the SSG reset signal is present (nominally on master_reset).

The 32-bit values in the ssg_bram are interpreted as follows:

  • bits 32 downto 5 - Duration of this state in spectrum ticks
  • bit 4 - Advanced Sig/Ref currently not used
  • bit 3 - Sig/Ref 1 currently not used
  • bit 2 - Sig/Ref 0 - gpioA bit 2 and LED 2
  • bit 1 - Cal - gpioA bit 1 and LED 1
  • bit 0 - Local Blank - gpioA bit 0 and LED 0

Note

As of 2012.03.09, the switching signals are generally not connected to the appropriate GPIO pins.

The external switching signals used in slave mode (from either the Master ROACH or another source) are taken from gpioB bits 2 downto 0 as follows:

  • bit 2 -

master_slave_sel

In ver 111, the bits of register ssg_master_slave_sel are defined as follows:

  • bit 7 - Select source of external blank signal
    • If zero, use ASR in
    • If one, use BLANK in
  • bit 6 - Enable ORing with external blank signal
  • bit 5 - Front panel LED control
  • bit 4 - Front panel LED control
  • bit 2 - Controls signals sent to gpio-A outputs
    • If zero, forward internally generated blanking signals to output gpio-A's (use this for the master when the master generates the signals)
    • If one, forward the computed status bits to the output. Use this for the master ROACH when receiving an external blanking signal from the LO.
  • bits 1 and 0 - Controls where the status bits in the output packet header comes from
    • If 00, status bits connected to output of internal SSG (for master generated signals, or master generating signals and ORing with external blank)
    • If 01, status bits connected to registered copy of bits received by gpio-B inputs (for master using all externally generated signals, no local blanking)
    • If 10, status bits connected directly to gpio-B inputs (for slave using signals from the SSG master).