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VEGAS Data Packet Format

The SPEAD protocol is designed to propagate changes in a set of variables from one location to another. SPEAD uses the UDP protocol to transmit data packets called datagrams from one computer or FPGA board to another. A single SPEAD HEAP consists of a SPEAD header, three or more optional (ItemPointer) fields and a packet payload. A single HEAP may be split over multiple UDP datagrams (packets). For more specifications check:1

VEGAS SPEAD Packet Specification for High-Bandwidth Modes

The following is the structure of the SPEAD HEAP for the high-bandwidth modes. For low-bandwidth modes (where the GPU does the spectroscopy), a different HEAP structure will be used. This alternative HEAP structure has not yet been determined.

• 8 bytes with information of the SPEAD header:

       0x5304`` ``0x0305`` ``0x0000`` ``0x0006

• 4x8 bytes with necessary SPEAD information: HEAP counter + HEAP size + HEAP offset + Packet payload length. Each of the item descriptors has:

       "first bit (1) + 23b (ID) + 40b (item value)"

• 6x8 bytes with the ItemGroup information.

       "first bit (0/1) + 23b (ID) + 40b(item value or offset)

  -
    \- **Time stamp:** This counter is incremented at the FPGA clock
    rate. The FPGA click is locked to the GBT maser via the ADC
    sample clock synthesizer. The counter is reset at the 1 PPS tick
    after an ARM command is issued.

  -
    \- **Spectrum counter:** The counter is incremented once per
    spectrum, even blanked spectra. It is reset on the 1 PPS tick
    after the ARM command is issued. The internal FPGA sync pulse
    generator is also reset on the same PPS after the ARM command is
    issued, so the spectra on all roach boards are synchronous.

  -
    \- **Number of spectra in integration:** this counter is
    incremented every spectrum, unless that spectrum is blanked. It
    is reset at the start of each FPGA integration. This counter
    therefore indicates the number of spectra that were integrated
    on the FPGA, before the integrated spectrum was transmitted to
    the HPC.

  -
    \- **Mode number:** the mode in which the FPGA is operating (as
    per the spectrometer modes defined in the GBT specification).

  -
    \- **Switching signals:** The first 36 first bits are set to 0.
    They can be used for another purpose in the future. The bottom 4
    bits reflect the state of the switching signals and the blanking
    bit.

  -
    \- **Payload data pointer:** 40 bits will indicate the offset
    into the heap where the data starts.

• Spectrum data with a variable length.

Spead_packet_v1.png

More information on how the spectra are packed into the packet payload can be found here: File:spead_format_high_bandwidth.pdf

VEGAS SPEAD Packet Specification for Low-Bandwidth Modes

For LBW modes, the packets contain time-domain samples, rather than spectra. The LBW packets are not SPEAD packets, and their format is as described below.

The structure of the header is as follows:

 ----------------------------------------------------------
| FGPA counter (60 bits)                 | status (4 bits) |
 ----------------------------------------------------------
| FGPA counter (60 bits)                 | status (4 bits) |
 ----------------------------------------------------------

The status bits remain the same in both the words, and the packet counter field increments by 1 between the two words. The HPC code looks only at the first word, and ignores the second. This is not an elegant design, but it worked, and we moved on to other things. Ideally, this will be fixed.